Cache Balancer: A communication latency and utilization aware resource manager

The increasing number of processors in today's many-core architectures has lead to new issues regarding memory management. The performance of many-core processors is often limited by the communication latency incurred in data transfers between different cores. Conventional memory allocators do not take such communication costs into account while...

Time Synchronization in Wireless Sensor Networks

Accurate time synchronization is crucial for many applications of Wireless Sensor Networks. Extensive research is performed on this topic, however, there are some aspects of time synchronization which still require attention. In this thesis we investigate aspects of the network which influence the accuracy of packed based time synchronization in...

MEP-MAS: A Message Passing Multiprocessor Array for Streaming Applications

This thesis presents the design and implementation of a Chip-Multiprocessor (CMP) targeted at streaming applications(e.g. MPEG, MP3). Streaming applications are applications which can be split into several distinct stages working on data elements in a pipelined fashion. We propose a distributed-memory array (MEP- MAS), where the cores...

System-level Fault-Tolerance Analysis of Small Satellite On-Board Computers

Commercial Off-The-Shelf (COTS) electronic components offer cost-effective solutions for the development of On-Board Computers (OBCs) in the small satellite industry. However, the COTS parts are not originally designed to withstand the space radiation environment. Traditional fault-tolerance practices rely on expensive radiation tests or are...

Design and analysis of a coherent memory sub-system for FPGA-based embedded systems

Cache coherence and memory consistency are of the most decisive and challenging issues in the design of shared-memory multi-core systems that influence both the correctness and performance of parallel programs. In this thesis, we identify and analyze the problem of designing a coherent/consistent memory subsystem in general and then focus on...

High-Quality, Real-Time HD Video Stereo Matching on FPGA

Stereo matching is an important computer vision technique, which extracts the depth information of the scene by matching a pair of stereo images. It has numerous applications, such as view-point interpolation, 3DTV, object detection, etc. In the past decades, many algorithms have been proposed to improve the matching quality or to increase the...

Design Partitioning for Custom Hardware Emulation

Hardware verification is a very important step of system design. Various techniques are used for this purpose one of which is hardware emulation. Hardware emulation is a very efficient and flexible technique with high speed performance in comparison to other approaches. Emulation using programmmable hardware can provide a very fast and feature...

Specification and Implementation of a DMA Controller in an Embedded System

The fast growing of In-Car entertainment application leads to an increasing challenge for both data computation and data communication, which are managed by the microprocessor. The thesis project is the third stage of a continuous Direct Memory Access(DMA) Controller project in NXP Semiconductors for the purpose of specifying and implementing a...

Desynchronization Methods for Scheduled Circuits

Synchronous systems waste a lot of power in the clock tree, and must be designed based on the worst case scenario in terms of speed. Asynchronous circuits offer relief to these problems, by replacing clock signals with handshakes which only charge when data is being transferred, and delay signals which may adapt more easily to variance in speed...