A 10Gb/s PI-CDR design

In this thesis the design and analysis of a dual-loop phase interpolator(PI) clock and data recovery(CDR) with a Delay locked loop (DLL) as a reference loop will be discussed.

A Doherty-Like Class-G HoC SCPA: With deep power back-off efficiency enhancement

An Energy-Efficient High-Speed Full-Duplex IR-UWB Transceiver For Joint Radar and Communication (RadCom)

In recent years, short-range reliable wireless system with high data rate and low power consumption has drawn sufficient attention and is in great demand in various applications. For biomedical implantable applications such as neural sensing and Brain-computer Interfaces (BCIs), due to the increasing number of sensing channels and elements, not...

A Highly Linear I/Q Interleaving DDRM: A 4GHz Low Power, Highly Linear I/Q Interleaving DDRM in 40nm CMOS Technology

In recent years, the demand for wireless communication devices is rapidly increasing and it is estimated to keep growing exponentially over the coming decade. This demand is accompanied by a demand for high-speed and reliable communication. One of the challenges faced by the RF design engineers is to fulfill these demands while utilizing the...

An energy-efficient, high-data-rate IR-UWB transmitter with hybrid modulation for brain-computer interfaces

In recent years, implantable neural sensing and Brain-computer Interfaces (BCIs)<br/>have manifested their potential in medical and clinical uses. However, their wide adoptions are impractical without reliable wireless telemetry systems for transmitting recorded neuron activities to external devices.

A High Efficiency Switched-Capacitor Power Amplifier with Real-Time Calibration for Harmonic Suppression

A switched-capacitor power amplifier (SCPA) is a very desirable solution to the problem of enabling amplitude modulation while utilizing high-efficiency switching PA topologies for non-constant envelope wireless RF signals, due to its highly linear AM curve, low complexity, and high scalability. However, drawbacks exist in the form of low...

Linear and Efficient Power Amplifier for WiFi

CMOS technology is one of the feasible solutions to meet the world’s growing demand for high data rates because it offers the prospect of SoC at a low cost. But, the PA forms the major bottleneck in making SoC because the PAs in high data rate wireless communication systems have the requirement of high-efficiency and good linearity even at...

A 10 Gbps Wireline Transceiver Link: To Interface Future RF-DACs

This thesis presents the development of circuits and systems for fast wireline transceiver links that will enable a move towards highly integrable RF digital-to-analog converters. A new perspective on the analysis of bit error rates in wireline links leads to the PAM spectral design space chart: a novel, visual system design analysis tool for...

An FM Chirp Waveform Generator and Detector for Radar: Baseband, intermediate frequency, low noise and RF power amplifiers

This report describes the design of different amplifiers that are part of an FM transceiver. This is part of a larger project, which has the objective to design a complete FM transceiver from discrete components only, meaning that IC technology is not considered. <br/>The circuits designed are two baseband amplifiers, an intermediate frequency...

Energy Efficient Wideband Supply Interpolating Transmitter for Millimeter-Wave 5G System

In 5G transmitters, high efficiency, high linearity, and compatibility with MIMO and beamforming techniques are of utmost importance. Typically, enhancement techniques like supply modulation or load modulation are used when dealing with envelope modulated communication signals, which increasingly have high peak-to-average-power ratios (PAPR)....

Power RF-DAC: The Design of a LDMOS Class-E SMPA DRAC with a CMOS Driver

Recent years have seen an exponential growth in required wireless data capacity. This exponential growth is expected to continue, while it is unsustainable if the power consumption associated with it will grow at the same rate. This calls for better power efficiency, which can usually be found in polar power amplifier architectures. This thesis...

Switched-Device Power Amplier using Bias Control

In this work, a switched-device power amplier using bias control is designed and realized. The PA operates at a frequency of 100MHz. Test results show that the PA achieves a PAE of 63% at −6dB power back-off and 60% at the peak output power of 40dBm. First, an overview of the state-of-the-art PA technology and performance in high PAPR...

Wideband Hybrid-Class Power Amplifier for Base Station Applications Using LDMOS with Envelope Tracking System

Conventional RF power amplifiers are normally designed for peak efficiency at maximum output power. However, for WCDMA application, the power amplifier often operates at 6-8 dB power back-off. Consequently, when the power is backed-off from its peak point, the efficiency of conventional power amplifier drops sharply. The envelope elimination and...