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Elsayed, A.H. (author)
In recent years, exciting new low-power design methods have been introduced, such as: multiple supply voltages, body bias techniques and power shut-off. In order to use these low power design methods, strict requirements for both libraries and tools are needed. An additional challenge is the introduction of more accurate characterization models...
master thesis 2012
document
Zheng, X.Y. (author)
Static Timing Analysis (STA) is one approach to verify the timing of a digital circuit. The currently used Gate Level Model (GLM) has limitations on performing STA for circuits when taking process variations into consideration. The transistor level model is developed taking the statistical factors into account. This thesis presents an...
master thesis 2012
document
Rodriguez Rodriguez de Guzman, J. (author)
Accurate timing analysis of digital integrated circuits is becoming harder to achieve with current and future CMOS technologies. The shrinking feature sizes lead to increasingly important local process variations (PV), making existing methods like corner-based static timing analysis (STA) yield overly pessimistic results. While industry faces...
master thesis 2012
document
Nigam, A. (author)
As we are moving toward nanometre technology, the variability in the circuit parameters and operating environment (Process, Voltage and Temperature (PVT)) are increasing, causing uncertainty in the circuit performance. Statistical Static Timing Analysis (SSTA) is a category of methodologies to analyse the variations in delay due to PVT...
master thesis 2010
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