Bit-error rate measurement setup and comparator design

Bit-error rate (BER) of comparators is becoming one of the limiting factors in the design of high speed ADCs. BER measurement setup is introduced and implemented in this thesis. Using this BER measurement setup gives us the opportunity to compare the BER of different comparators. It also enables us to study the effect of different parameters...

A 12-bit 500MS/s Pipeline Split-ADC

"Split-ADC" calibration is a recently proposed digital background calibration architecture. It requires a much lower number of cycles to calibrate the ADC errors due to its deterministic nature, without placing any additional analog complexity. While new error estimation techniques are being explored using this architecture through simulations,...

A Low-Power Class-AB Residue Amplifier for a 12bit 500MS/sec Pipeline ADC with Digital Calibration

This work mainly focuses on designing a low-power class-AB residue amplifier for a 12bit 500MS/sec pipeline ADC with digital calibration. A foreground ideal calibration test bench has been implemented in MATLAB to correct non-linearities of the amplifier up to the 5th order. A detailed comparison has been made between a class-A amplifier and a...

A low noise, low power dynamic amplifier with common mode detect and a low power, low noise comparator for pipelined SAR-ADC

This thesis presents a high gain, low noise and low power dynamic residue amplifier and a low power, low noise dynamic comparator designed in TSMC 28nm process for a two step Pipelined SAR-ADC. The cascoded integrator dynamic residue amplifier (CIDRA) achieves a gain of 30dB with THD of 47dB (11 mV pp input). The input referred noise across tem-...

Sampling time error calibration in Time-interleaved ADCs

A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s SAR-Assisted Pipeline ADC

Voltage reference buffers have always been the most power-hungry blocks in switched-capacitor SAR ADCs. High frequency dynamic loading of the buffer by the capacitive DAC causes glitches on the reference voltage, and the buffer has to be fast enough to recover such transients to 1/2 LSB precision in every bit cycle. Such stringent requirements...

Resistor-Based Digital-to-Analog Converters

Transmit digital-to-analog converters have become an essential building block for state-of-the-art Ethernet infrastructures. They are also one of the most significant sources of power consumption in an Ethernet physical layer (PHY) transceiver. These devices must maintain high linearity and a well-defined impedance of 100 Ω while operating at a...