A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s SAR-Assisted Pipeline ADC

Voltage reference buffers have always been the most power-hungry blocks in switched-capacitor SAR ADCs. High frequency dynamic loading of the buffer by the capacitive DAC causes glitches on the reference voltage, and the buffer has to be fast enough to recover such transients to 1/2 LSB precision in every bit cycle. Such stringent requirements...

Bit-error rate measurement setup and comparator design

Bit-error rate (BER) of comparators is becoming one of the limiting factors in the design of high speed ADCs. BER measurement setup is introduced and implemented in this thesis. Using this BER measurement setup gives us the opportunity to compare the BER of different comparators. It also enables us to study the effect of different parameters...