Searched for: contributor%3A%22Goossens%2C+K.G.W.+%28promotor%29%22
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Beyranvand Nejad, A. (author)
Recent trends show a steady increase towards concurrently executing more and more applications on a single embedded system. Multi-Processor System-on-Chip (MPSoC) architectures are proposed to allow complex design of embedded systems. This is achieved by integrating as many processing resources as possible on a single chip and therefore enabling...
doctoral thesis 2014
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Zaykov, P.G. (author)
In this dissertation, we address the problem of performance efficient multithreading execution on heterogeneous multicore embedded systems. By heterogeneous multicore embedded systems we refer to those, which have real-time requirements and consist of processor tiles with General Purpose Processor (GPP), local memory, and one or more...
doctoral thesis 2014
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Chandrasekar, K. (author)
Embedded systems have become an integral part of our life in the last few years in multifarious ways, be it in mobile phones, portable audio players, smart watches or even cars. Most embedded systems fall under the category of consumer electronics, such as televisions, mobile devices, and wearable electronics. With several players competing in...
doctoral thesis 2014
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Mirzoyan, D. (author)
doctoral thesis 2013
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Wahlah, M.A. (author)
Technology down-scaling and platform-based designs have enforced a number of application and architecture trends for system-on-chip (SOC) designs. A modern SOC is now a multi-functional machine that can execute a large number of complex applications by using tens or even hundreds of intellectual properties (IPs). Meanwhile, due to a number of...
doctoral thesis 2012
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Stefan, R.A. (author)
One of the challenges of engineering is to make the best possible use of the available resources, or in other words allocating the resources in such a way as to maximize the overall profit. In the context of networks on chip the resources are represented by the communication bandwidth and the final profit is the performance of an application...
doctoral thesis 2012
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Hur, J.Y. (author)
This thesis presents our investigations on how to efficiently utilize on-chip wires to improve network performance in reconfigurable hardware. A fieldprogrammable gate array (FPGA), as a key component in a modern reconfigurable platform, accommodates many-millions of wires and the on-demand reconfigurability is realized using this abundance of...
doctoral thesis 2011
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Meenderinck, C.H. (author)
In pursuit of ever increasing performance, more and more processor architectures have become multicore processors. As clock frequency was no longer increasing rapidly and ILP techniques showed diminishing results, increasing the number of cores per chip was the natural choice. The transistor budget is still increasing and thus it is expected...
doctoral thesis 2010
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De Langen, P.J. (author)
doctoral thesis 2009
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Galuzzi, C. (author)
In this dissertation, we address the design of algorithms for the automatic identi?cation and selection of complex application-speci?c instructions used to speed up the execution of applications on recon?gurable architectures. The computationally intensive portions of an application are analyzed and partitioned in segments of code to execute in...
doctoral thesis 2009
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Molnos, A.M. (author)
doctoral thesis 2009
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Duarte, F. (author)
This dissertation presents a hardware accelerator that is able to accelerate large (including non-parallel) memory data movements, in particular memory copies, performed traditionally by the processors. As todays processors are tied with or have integrated caches with varying sizes (from several kilobytes in hand-held devices to many megabytes...
doctoral thesis 2008
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Shahbahrami, A. (author)
In this dissertation, a novel SIMD extension called Modified MMX (MMMX) for multimedia computing is presented. Specifically, the MMX architecture is enhanced with the extended subwords and the matrix register file techniques. The extended subwords technique uses SIMD registers that are wider than the packed format used to store the data. The...
doctoral thesis 2008
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Sourdis, I. (author)
This dissertation deals with essential issues pertaining to high performance processing for network security and deep packet inspection. The proposed solutions keep pace with the increasing number and complexity of known attack descriptions providing multi-Gbps processing rates. We advocate the use of reconfigurable hardware to provide...
doctoral thesis 2007
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Kachris, C. (author)
This dissertation presents our investigation on how to efficiently exploit reconfigurable hardware to design flexible, high performance, and power efficient network devices capable to adapt to varying processing requirements of network applications and traffic. The proposed reconfigurable network processing platform targets mainly access, edge,...
doctoral thesis 2007
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Fernandes Chaves, R.J. (author)
This thesis proposes a Secure Computing Module (SCM) for reconfigurable computing systems. SC provides a protected and reliable computational environment, where data security and protection against malicious attacks to the system is assured. SC is strongly based on encryption algorithms and on the attestation of the executed functions. The use...
doctoral thesis 2007
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Calderon Rocabado, D.R.H. (author)
In this dissertation, we address the design of multi-functional arithmetic units working with the most common fixed-point number representations, namely: unsigned, sign-magnitude, fractional, ten's and two's complement notations. The main design goal is to collapse multiple complex arithmetic operations into a single, universal arithmetic unit,...
doctoral thesis 2007
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Antochi, I. (author)
In this dissertation, we address low-power high performance 3D graphics accelerator architectures. The purpose of these accelerators is to relieve the burden of graphical computations from the main processor and also to achieve a better energy efficiency than can be achieved by executing these computations on the main processor. Since external...
doctoral thesis 2007
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