A High Speed DAC Architecture for Continuous Time Pipeline ADC

This thesis provides an investigation of the architecture and the design of the coarse DACs in continuous time pipeline (CTP) ADC to achieve high SFDR performance within a large bandwidth at sampling frequency of 4.8 GHz in TSMC 28nm technology.<br style="box-sizing: border-box"/> Mismatch errors of the coarse DACs in CTP ADC are very...