A Capacitance-Based Reference Scheme for a 14b-Linear, 100 MS/s SAR-Assisted Pipeline ADC

Voltage reference buffers have always been the most power-hungry blocks in switched-capacitor SAR ADCs. High frequency dynamic loading of the buffer by the capacitive DAC causes glitches on the reference voltage, and the buffer has to be fast enough to recover such transients to 1/2 LSB precision in every bit cycle. Such stringent requirements...

Design of a Baseband Section for LTE-Advanced Mobile Communiation

Design of LNTA for Multi-Band WCDMA

Currently, a low cost, single-chip multi-band WCDMA/GSM transceiver is needed for the 3G segment of the cellular communication that provides backward compatibility with the 2G GSM network. In this thesis, a novel, multi-band, low noise transconductance amplifier (LNTA) is presented. The LNTA has three stages, which are the transconductance,...

Modeling and design of integrated tunable patch reflector array for mm-wave antennas.

Millimeter wave sensor and communication technology may prove to be one of the key technologies of the 21st century covering a broad range of applications including high-speed telecommunication, medical diagnostics and security. The ultimate (commercial) success of these systems depends on their monolithic integration which brings about...

WideBand PLL as a clock multiplier

In this study, the theory, design and analysis of PLL circuits are examined and a 4.9GHz ~ 5.9GHz Wideband CMOS PLL Frequency Synthesizer is designed and implemented in IBM 65nm digital-process. The objective of this thesis work is to understand the limitations in Wideband PLL systems when the application frequency range extends to multiple...

Design of LNA+Mixer for Multi-Band WCDMA

A small, low-cost, single-chip multi-band WCDMA/GSM transceiver solution is needed to address the high growth segment of 3G enabled smart phone ICs, while still keeping compatibility with widely deployed 2G GSM networks. In this thesis, an inductor-less LNA+mixer combination for multi-band WCDMA is presented. By designing the mixer for high IIP2...

Bit-error rate measurement setup and comparator design

Bit-error rate (BER) of comparators is becoming one of the limiting factors in the design of high speed ADCs. BER measurement setup is introduced and implemented in this thesis. Using this BER measurement setup gives us the opportunity to compare the BER of different comparators. It also enables us to study the effect of different parameters...

Transmission Power Adaptation Using Link Quality Estimation In IEEE802.11

Nowadays, energy saving for wireless communication is more important than before. Lots of wireless devices are battery operated, like devices used in WLAN, ad hoc mode, sensor network, cellular network and so on. For example, Ad hoc networks which are composed of these wireless mobile devices can automatically establish peer to peer...

FMCW radar receiver front-end design

The main focus of this thesis is the design a receiver frontend for FMCW radar applications. In these systems, the increasing requirements on detection resolution,points towards the use of higher frequencies. In view of this, frequencies at W-band are very attractive due to the otential of high spatial resolution, while chip size and antennas...

Design of a Distributed Clock Generator for Multiple Power Domain System-on-Chip Integrated Circuits

Modern system-on-chip IC designs show great requirement on minimizing power consumptions. One of the low power techniques is using dynamic voltage frequency scaling for each power domain. Yet the clock generator unit is the bottleneck to apply this technique. In this thesis, we focus on the local clock generator unit solution and design three...