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Al-Ahdab, S. (author)
When the heart does not function properly, an artificial pacemaker is needed to correct the heart beat. However, more functionality at limited budget requires less power per function. Therefore, the power consumption of the pacemaker has to be reduced. The analog to digital converter in the pacemaker consumes the largest amount of power in the...
master thesis 2009
document
Wang, J. (author)
a 4-bit 250MHz sampling rate pipelined A/D converter, with 1.5-bit resolution per stage, has been designed by Cadence using TSMC 0.13um CMOS process. The ADC which works at 1.2 V supply voltage dissipates 15.23 mW and has an ENOB of 3.7 bits @ 100MHz sampling condition. The maximum DNL is 0.38 LSB, and the maximum INL is 0.352 LSB
master thesis 2009