DTC and TDC IC Design for Ultra-Low-Power ADPLL

The technology scaling favors the Digital PLLs, which is reconfigurable. In the traditional fractional-N ADPLL, whether counter-based or divider based, DCO and TDC are the main two power consuming blocks. Modifying the phase detection part based on phase prediction makes the architecture more energy-efficient. The new architecture leads to the...

Time-of-Flight 3D Imaging based on a SPAD-TDC Pixel Array in Standard 65 nm CMOS Technology

The interest in high performance three-dimensional (3D) imaging has grown in recent years due to immense demand in engineering, science, medicine and entertainment domains. The driving goals of state-of-the-art 3D imagers are high sensitivity to light and fine depth resolution at long range. Furthermore, high level of integration is desirable to...

Time-to-Digital Converter (TDC) for WiMAX ADPLL in State-of-The-Art 40-nm CMOS

WiMAX (Worldwide Interoperability for Microwave Access) is the emerging wireless technology standard of the near future, which enables high speed packet data access. To anticipate the future demands on WiMAX technology, we proposed an ADPLL (all-digital phase locked loop) solution for the WiMAX system. The developed ADPLL system has targeted...