Searched for: contributor:"van Leuken, Rene (mentor)"
(1 - 12 of 12)
document
Bhoera, Ramkoemar (author)
Global AIS coverage is not possible with terrestrial AIS as base stations are required to be build on sea, which is impractical. With the use of LEO satellites, the field of view of a single receiver is increased and is capable of communicating with many AIS cells simultaneously. As many vessels are transmitting data to the same receiver,...
master thesis 2019
document
Coenen, Joris (author)
One of the challenges of neuromorphic computing is efficiently routing spikes from neurons to their connected synapses. The aim of this thesis is to design a spike-routing architecture for flexible connections on single-chip neuromorphic systems. A model for estimating area, power consumption, memory, spike latency and link utilisation for...
master thesis 2019
document
Cangga Putra, Reynaldi (author)
DTB Multiplexer is a component within an NXP chip called the BAP3. This component provides a testing functionality for the chip. This component is purely combinational, and requires no clock, however this makes the component wiring-costly. This high wiring requirement leads to the area constraint imposed by the wiring demand rather than cell...
master thesis 2019
document
Mes, Johan (author)
The Self-Organizing Map (SOM) is an unsupervised neural networktopology that incorporates competitive learning for the classicationof data. In this thesis we investigate the design space of a system incorporating such a topology based on Spiking Neural Networks (SNNs), and apply it to classifying electrocardiogram (ECG) beats. We present novel...
master thesis 2018
document
Ardelean, Andrei (author)
Simulating large spiking neural networks (SNN) with a high level of
realism in a field programmable gate array (FPGA) requires efficient
network architectures that satisfy both resource and interconnect constraints, as well as changes in traffic patterns due to learning processes.
Based on a clustered SNN simulator concept, in this...
master thesis 2017
document
Joshi, Ayush (author)
Partial Discharges(PD) are commonly produced in defects within the insulation systems of high voltage equipment. These discharges are typically nanosecond current pulses in the amplitude range of milli-amperes. A long term exposure of the insulation system to these partial discharges accelerate the aging mechanisms that eventually lead to the...
master thesis 2017
document
Lin, Haipeng (author)
The high level of realism of spiking neuron networks and their complexity require a considerable computational resources limiting the size of the realized networks. Consequently, the main challenge in building complex and biologically accurate spiking neuron network is largely set by the high computational and data transfer demands. In this...
master thesis 2017
document
You, Xuefei (author)
Neuromorphic engineering, aiming at emulating neuro-biological architectures in efficient ways, has been widely studied both on com- ponent and VLSI system level. The design space of neuromorphic neuron, the basic unit to conduct signal processing and transmission in nervous system, has been widely explored while that of synapse, the specialized...
master thesis 2017
document
Stienstra, Ester (author)
In this thesis a prototyping system on chip of a 32 x 32 spiking neural network is presented. This network has been designed in UMC 65. In order to determine which neuron model to use three different analog CMOS neuron models are studied. One of these models is used in the network. The network consists of arrays of synapses and neurons, 32...
master thesis 2017
document
Zhang, Shizhao (author)
This thesis proposes a low-cost high-efficiency source-synchronous interface for high-speed inter-chip communication. The interface is composed of LVDS transceivers as external I/O buffers, and an all-digital data recovery, which can calibrate the received data phase to be aligned to the 90 phase of the received half-rate reference...
master thesis 2017
document
Zhang, HE (author)
The scalable simulation of neuron communication needs a large
amount of computing resources. The high throughput of data cause
the high requirement of interconnect network. This thesis is aimed
at the finding the efficient multi-FPGA connection for the neuron
network. First describe the characteristics of the network in terms
master thesis 2017
document
Jeyachandra, Evelyn Rashmi (author)
As technology scaling enters the nanometer regime, device aging effects cause quality and reliability issues in CMOS Integrated Circuits (ICs), which in turn shorten its lifetime. Evaluating system aging through circuit simulations is very complex and time consuming. In this thesis, a framework is proposed, which allows for the evaluation of...
master thesis 2017
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