Self-timed interconnect for SNN - From Point to Point Communication to Multi-array Segmented-bus Solution

Spiking Neural Networks use Address Event Representation to communicate among different Neuron Arrays. To mimic the behavior of the human neural system and meets the requirement for large Neuron Array communication, the AER interconnect should be area-saving, have low power, and operates at high speed.<br/>This thesis aims to build self-timed...

Source-Synchronous Interface with All-Digital Data Recovery: A Low-cost Efficient Design

This thesis proposes a low-cost high-efficiency source-synchronous interface for high-speed inter-chip communication. The interface is composed of LVDS transceivers as external I/O buffers, and an all-digital data recovery, which can calibrate the received data phase to be aligned to the 90^◦ phase of the received half-rate reference...

Multi-FPGA Interconnect Simulation

The scalable simulation of neuron communication needs a large<br/>amount of computing resources. The high throughput of data cause<br/>the high requirement of interconnect network. This thesis is aimed<br/>at the finding the efficient multi-FPGA connection for the neuron<br/>network. First describe the characteristics of the network in terms<br/...