Searched for: contributor:"Wong%2C%5C J.S.S.M.%5C %5C%28mentor%5C%29"
(1 - 17 of 17)
document
Heida, W.F. (author)
As predicted by Gordon E. Moore in 1975, the number of transistors has doubled every two years over the last decades. This technology scaling led to a higher performance of Integrated Circuits (ICs) like processors, but have also made these devices more susceptible to Single Event Effects (SEEs). SEEs are caused by transistors changing state...
master thesis 2016
document
Yousaf, M.M. (author)
Autonomous mobile robots generally have limited computational power on-board, and they have to perform their tasks in real-time in order to interact with their surroundings effectively. Therefore, there is a need to utilize the available computational capabilities efficiently. The ρ-VEX is a run-time reconfigurable VLIW processor. This unique...
master thesis 2016
document
Gupta, R.K. (author)
Electronic companies are increasingly using field-programmable gate arrays in various domains such as application acceleration, complex digital designs or ASIC prototyping. The Verification phase holds a significant place in the FPGA design development process. A key challenge during verification is observability. This is defined as the ability...
master thesis 2015
document
Van der Wijst, H. (author)
In recent years the use of co-processors to accelerate specific tasks is becoming more common. To simplify the use of these accelerators in software, the OpenCL framework has been developed. This framework provides programs a cross-platform interface for using accelerators. The ?-VEX processor is a run-time reconfigurable VLIW processor. It...
master thesis 2015
document
Meun, K. (author)
Increased technology scaling not only resulted in a performance increase of the microprocessor, but also led to increasing device vulnerability to external disturbances. Scaling accelerates ageing induced failures of CMOS devices and the average lifetime of electronic devices diminishes. This thesis describes the design and implementation of a...
master thesis 2015
document
De Wit, R. (author)
The design of a protocol parser in hardware based on language theory to improve time-to-market, reduce development cost and increase performance compared to protocol parsing in software.
master thesis 2015
document
Andronikidis, G. (author)
Embedded Reconfigurable Architectures (ERA) is a project with the objective to design a platform that combines reconfigurable computing and network elements which can adapt on-the-fly their composition, organization and even instruction-set architectures in an effort to provide the best possible trade-offs in performance and power for the given...
master thesis 2014
document
Reda, M.B. (author)
The ?-VEX processor is a parameterized reconfigurable Very Large Instruction Word (VLIW) softcore processor. It can be reconfigured in the issue-width, number and type of functional units (FUs), width of memory buses and number of registers in the multi- ported register file. The current design of the ?-VEX processor supports single cluster...
master thesis 2014
document
Hoozemans, J.J. (author)
This thesis describes the design and implementation of an FPGA-based hardware platform based on the rVEX VLIW softcore and the adaption of a Linux 2.0 no_mmu kernel to run on that platform. The rVEX is a runtime reconfigurable VLIW softcore processor. It supports various configurations that allow programs to run faster or more efficient. The...
master thesis 2014
document
De Zeeuw, M. (author)
Developments in reconfigurable platforms result in constantly increasing available area and improving technology. These improvements allow embedded systems to implement increasingly complicated systems. As a result the performance gap of processors build on FPGA technology compared to Semi-custom ASIC technology is decreasing. The down side of...
master thesis 2011
document
Kong, Q. (author)
In this thesis, we present a design of interrupt system upon an extensible and reconfigurable VLIW softcore processor: r-VEX. This interrupt system is designed and implemented in four mechanisms to match different application requirements in terms of the hardware consumption and performance issues (interrupt latency). On the other hand, due to...
master thesis 2011
document
Brandon, A.A.C. (author)
In this thesis we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. In order for our solution to be generic, as opposed to related ISA extension approaches, we insert system calls into the original program to control the...
master thesis 2010
document
Seedorf, R.A.E. (author)
The speed gap between a processor realized in Semi-custom ASIC technology and a processor realized in FPGA technology is narrowing. In processor design, the approach is to define the microarchitecture of the processor and to design and implement it for executing an application domain. In this thesis, we have investigated the approach to design a...
master thesis 2010
document
Bieleveld, M.J.M. (author)
This thesis is part of the Arachne project which focusses on novel processor architectures that enable an ubiquitous and unobtrusive communication environment. Nowadays, the Internet provides many services of which some are envisioned to be utilized by stand alone devices. Access to those services requires an Internet Protocol stack (IP)...
master thesis 2010
document
Krijgsman, S. (author)
As the area of applications for Field Programmable Gate Arrays, or FPGAs, continues to expand, designers are searching for new methods to enhance the flexibility and efficiency of these devices. A technique called Dynamic Partial Reconfiguration is based on a principle of reconfiguring a small region of the FPGA, while the remainder of the...
master thesis 2009
document
Van As, T. (author)
Increasingly more computing power is being demanded in the domain of multimedia applications. Computer architectures based on reconfigurable hardware are becoming more popular now that classical drawbacks are diminishing. FPGA are constantly improving in terms of performance and area, and provide a technology platform that allows fast and...
master thesis 2008
document
Raaijmakers, S.J. (author)
Reconfigurable Computing entails the utilization of a general-purpose processor augmented with a reconfigurable hardware structure (e.g. a field-programmable gate array). Normally, a complete reconfiguration is needed to cha nge the functionality of the FPGA even when the change is only minor. Moreover, the complete chip needs to be halted to...
master thesis 2007
Searched for: contributor:"Wong%2C%5C J.S.S.M.%5C %5C%28mentor%5C%29"
(1 - 17 of 17)