A 1 GSa/s Deep Cryogenic, Reconfigurable Soft-core FPGA ADC for Quantum Computing Applications

Analog interfacing is the only way to communicate with a quantum processor, whether it is applying qubit operations or reading their quantum states. There exist other applications where analog interfacing is abundant, e.g. sensor networks, automotive, industrial control, etc. In those applications the use of FPGAs is continuously growing,...

Hardware Acceleration of BWA-MEM Genome Mapping Application

Next Generation Sequencing technologies have had a tremendous impact on our understanding of DNA and its role in living organisms. The cost of DNA sequencing has decreased drastically over the past decade, leading the way for personalised genomics. Sequencers provide millions of fragments of DNA (termed short reads), which have to be aligned...

Hardware Acceleration of Monte-Carlo Integration in Finance

This thesis describes FPGA-accelerated Monte-Carlo integration using adaptive stratified sampling. Monte-Carlo integration can be used to determine the value of integrals that have no closed form solution. In this work, the FPGA-accelerated design is used to determine the price of different types of financial options. The considered options are...

Development of a Multichannel TCSPC System in a Spartan 6 FPGA LinoSPAD - Fluorescence Lifetime Imaging for Fluorescence Guided Surgery

For the master project work was carried out for the development of a fluorescence lifetime imaging probe for fluorescence guided surgery. For this project a prototype was designed. The work on the prototype was divided into three main parts, hardware, firmware / software, and system / optics. In this thesis the firmware / software of the system...

Performance Improvement of Optical Algorithms on Multicore Platforms

ASML is one of the world's largest suppliers of lithography systems for the semiconductor industry. ASML designs and develops machines that are used to print circuits on silicon wafers, to produce IC chips. These circuits have to be printed with accuracy of up to 2nm. For this purpose, the machines incorporate several measurement systems. The...

Low-Cost Smith-Waterman Acceleration

Due to advancing technology, genetic sequencing has become cheaper over the years. This has caused the demand for computational power to grow even faster than Moore's law. To remedy this problem, we analyzed low-cost hardware solutions to parallelize the computational part of the genetic sequencing. We proposed a novel method for calculating the...

Towards high-level synthesis of neural models on FPGAs

Recent trends in studying the brain activity have attracted interest in the simulation of neurons to understand the brain functionality. However, these simulations are computationally intensive and time consuming, which limits this study. High-performance FPGA-based platforms are being utilized to accelerate these simulations. However, the...

Acceleration of Fingerprint Minutiae Extraction Using a VLIW Processor

Deze scriptie beschrijft het ontwerp van een embedded systeem dat de kenmerkende eigenschappen uit de afbeelding van een vingerafdruk haalt. Het betreft een hardware/software codesign, waarbij een VLIW-processor als accelerator is gebruikt.

High-Quality, Real-Time HD Video Stereo Matching on FPGA

Stereo matching is an important computer vision technique, which extracts the depth information of the scene by matching a pair of stereo images. It has numerous applications, such as view-point interpolation, 3DTV, object detection, etc. In the past decades, many algorithms have been proposed to improve the matching quality or to increase the...

Interrupt support on the ?-VEX processor

In this thesis, we present a design of interrupt system upon an extensible and reconfigurable VLIW softcore processor: r-VEX. This interrupt system is designed and implemented in four mechanisms to match different application requirements in terms of the hardware consumption and performance issues (interrupt latency). On the other hand, due to...

An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service

Prototyping Systems on Chip (SoC) on FPGA technology improves the time that the de- signer needs to spend in the verification stage when developing new systems or upgrading the existing ones. However, FPGA prototyping is very challenging due to the few resources available in this chips, and often the large designs do not fit into one single FPGA...

Data Acquisition System Design for a 160x128 Single-photon Image Sensor with On-pixel 55 ps Time-to-digital Converter

Time-resolved image sensors enabling picosecond resolutions over large formats are needed in many advanced imaging fields, from fluorescence lifetime imaging microscopy (FLIM) to positron emission tomography (PET). Integrated single-photon avalanche diode (SPAD) technology embodies the new frontiers of time-resolved imaging, namely better...

Fingerprint Verification on the VEX Processor

The speed gap between a processor realized in Semi-custom ASIC technology and a processor realized in FPGA technology is narrowing. In processor design, the approach is to define the microarchitecture of the processor and to design and implement it for executing an application domain. In this thesis, we have investigated the approach to design a...

Reconfigurable Trigger Logic for Electronic Instrumentation in Space Applications

Future space missions have to rely on advanced, smart and very light payloads in order to explore the solar system within a reasonable cost envelope. For this reason, efforts are made to obtain higher levels of integration that can reduce costs and allow the presence of more and more instruments on board of small spacecrafts. With the advent of...

IWEX: Mapping on current high performance architectures

IWEX stands for Invers Wavefield Extrapolation and is commonly used in seismic exploration. Niels Pörtzgen[15] showed that this technique can also be used for inspection of welds. This thesis describes two domains in which the IWEX algorithm can be calculated. The time domain which has a quantization problem and the frequency domain which is...

Protocol conversions for the Aethereal Networks-on-Chip

Bus based interconnects are commonly used to connect Intellectual Properties (IPs) on System-on-Chip (SoC). However, as the number of high performance IPs with large communication requirements in a Multi Processor SoC (MPSoC) increases, the bus interconnects become a communication bottleneck. To overcome this limitation, the bus based...

Feasibilty Analysis for Hardware Acceleration of Pattern Recognition Algorithms

This thesis presents a feasibility analysis for hardware acceleration of the pattern recognition algorithms used by the Media Knowledge Engineering department at the Delft University of Technology. The feasibility analysis is conducted on a number of different algorithm classes. The Parzen Window algorithm appeared to be the most suitable option...