Device-Aware Test for Back-Hopping Defects in STT-MRAMs

The development of Spin-transfer torque magnetic RAM (STT-MRAM) mass production requires high-quality dedicated test solutions, for which understanding and modeling of manufacturing defects of the magnetic tunnel junction (MTJ) is crucial. This paper introduces and characterizes a new defect called Back-Hopping (BH); it also provides its...

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs

The manufacturing process of STT-MRAM requires unique steps to fabricate and integrate magnetic tunnel junction (MTJ) devices which are data-storing elements. Thus, understanding the defects in MTJs and their faulty behaviors are paramount for developing high-quality test solutions. This article applies the advanced device-aware test to...

MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design

The popularity of perpendicular magnetic tunnel junction (pMTJ)-based spin-transfer torque magnetic random access memories (STT-MRAMs) is growing very fast. The performance of such memories is very sensitive to magnetic fields, including both internal and external ones. This article presents a magnetic-field-aware compact model of pMTJ, named...

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs

Understanding the manufacturing defects in magnetic tunnel junctions (MTJs), which are the data-storing elements in STT-MRAMs, and their resultant faulty behaviors are crucial for developing high-quality test solutions. This paper introduces a new type of MTJ defect: synthetic anti-ferromagnet flip (SAFF) defect, wherein the magnetization in...

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM

Understanding the defects in magnetic tunnel junctions (MTJs) and their faulty behaviors are paramount for developing high-quality tests for STT-MRAM. This paper characterizes and models intermediate (IM) state defects in MTJs; IM state manifests itself as an abnormal third resistive state, apart from the two bi-stable states of MTJ. We...

Defect and Fault Modeling Framework for STT-MRAM Testing

STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This article presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate...

Device-Aware Test: A New Test Approach Towards DPPB Level

This paper proposes a new test approach that goes beyond cell-aware test, i.e., device-aware test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT development. The defect modeling does not assume that a defect in a device (or a cell) can be modeled electrically as a linear resistor (as the traditional approach...