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Yanik, K.I.M. (author)
The trend of increasing performance by parallelism is followed by the adoption of heterogeneous systems. In order to allow more fine-tuned balancing between used thread- and instruction level parallelism, the heterogeneous ρ-VEX platform was developed. Pipelining has been a part of microprocessor development for decades to increase throughput of...
master thesis 2016
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Johansen, J. (author)
The ?-VEX is a run-time reconfigurable Very Long Instruction Word (VLIW) processor. This unique processor allows separation of its issue lanes to form independently operating processing cores. Switching between these configuration during run-time allows optimizing the platform for the task(s) it is performing. Porting an Operating System (OS) to...
master thesis 2016
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Meun, K. (author)
Increased technology scaling not only resulted in a performance increase of the microprocessor, but also led to increasing device vulnerability to external disturbances. Scaling accelerates ageing induced failures of CMOS devices and the average lifetime of electronic devices diminishes. This thesis describes the design and implementation of a...
master thesis 2015
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Iorga, D. (author)
Numerous applications from autonomous vehicles to surveillance systems can benefit from "seeing in 3D". A crucial element of sight is depth detection since this enables evaluation of position and shape. The depth at which objects are located can be estimated by using two or more cameras and comparing the resulting images. Despite the increasing...
master thesis 2015
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Andronikidis, G. (author)
Embedded Reconfigurable Architectures (ERA) is a project with the objective to design a platform that combines reconfigurable computing and network elements which can adapt on-the-fly their composition, organization and even instruction-set architectures in an effort to provide the best possible trade-offs in performance and power for the given...
master thesis 2014
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Hoozemans, J.J. (author)
This thesis describes the design and implementation of an FPGA-based hardware platform based on the rVEX VLIW softcore and the adaption of a Linux 2.0 no_mmu kernel to run on that platform. The rVEX is a runtime reconfigurable VLIW softcore processor. It supports various configurations that allow programs to run faster or more efficient. The...
master thesis 2014
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Shankar, A. (author)
A clustered architecture is a viable design choice when aiming to increase the performance of a VLIW processor while avoiding the hardware complexity and increased access times associated with a centralized register file. However, this places additional responsibility on the compiler: the production of an efficient cluster assignment. In this...
master thesis 2013
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Okmen, Y. (author)
In the last decade, the importance of graphics capabilities have become very important in the mobile market. As a result low power embedded solutions for mobile devices have been eveloped to run computationally intensive graphics applications, which extensively uses floating point calculations. The work proposed in this thesis target the...
master thesis 2011
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Purba, M.S.B. (author), Yigit, E. (author), Regeer, A.J.J. (author)
Deze scriptie beschrijft het ontwerp van een embedded systeem dat de kenmerkende eigenschappen uit de afbeelding van een vingerafdruk haalt. Het betreft een hardware/software codesign, waarbij een VLIW-processor als accelerator is gebruikt.
bachelor thesis 2011
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De Zeeuw, M. (author)
Developments in reconfigurable platforms result in constantly increasing available area and improving technology. These improvements allow embedded systems to implement increasingly complicated systems. As a result the performance gap of processors build on FPGA technology compared to Semi-custom ASIC technology is decreasing. The down side of...
master thesis 2011
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Van den Broeke, G. (author), Mul, D.P.N. (author)
Deze scriptie betreft een onderzoek naar het versnellen van een JPEG-decoder in een embedded systeem. Hierbij wordt de ?-VEX VLIW-processor als accelerator gebruikt. Onderzocht wordt hoe de hardware en software aan elkaar kunnen worden aangepast om de applicatie zo snel mogelijk uit te voeren.
bachelor thesis 2011
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Seedorf, R.A.E. (author)
The speed gap between a processor realized in Semi-custom ASIC technology and a processor realized in FPGA technology is narrowing. In processor design, the approach is to define the microarchitecture of the processor and to design and implement it for executing an application domain. In this thesis, we have investigated the approach to design a...
master thesis 2010
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Trienekens, R. (author)
Applications run on embedded DSPs become increasingly complex, while the demands on speed and power continue to grow. One method of meeting these demands is to move some of the processor complexity from hardware to the compiler. This increases the importance of the role of the compiler. This thesis describes how we ported the Gnu Compiler...
master thesis 2009
Searched for: faculty%3A%22Electrical%255C%252BEngineering%252C%255C%252BMathematics%255C%252Band%255C%252BComputer%255C%252BScience%22
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