Towards high-level synthesis of neural models on FPGAs

Throughput and Power optimization of the Range Trie design for IP lookups

Simdization transformation strategies

Integration of existing optimisation techniques with the DWARV C-to-VHDL compiler

Asynchronous Logic as Counter Measure against Power Analysis Attacks

Fault-Tolerant On-Board Computer Software for the Delfi-n3Xt Nanosatellite

An Adaptive Defect-Tolerant Multiprocessor Array Architecture

A Novel Concurrent Validation Scheme for Hardware Transactional Memory

Dead code elimination for web applications written in dynamic languages

Hardware and algorithm study for a fingerprint verification system

Reordering DRAM Requests for Improved Bandwidth Utilization

End User Involvement in Exploratory Test Automation for Web Applications

Architecture-Level Fault-Tolerance Techniques for Biomedical Implants

On 3D Stacked IC Yield Improvement and 3D-DfT Test Architecture

Nonblocking Distributed State-Tree-Structures

Performance estimation technique for optimizing and integrating IPs in MPSoCs

Tile-Based rasterization on an embedded Tile-based MPSoC

Throughput-constrained Voltage and Frequency Scaling for Real-time heterogeneous multiprocessors

Offloading mobile data traffic to Wi-Fi through MASS-ANET: Mobile assisted ad-hoc networking

System Level Support for Dynamic Partial Reconfiguration