Searched for: subject%3A%22%255C%253F%255C-VEX%22
(1 - 1 of 1)
document
Van Straten, J. (author)
This thesis describes the design and implementation of a VLIW processor and associated caches based on the ρ-VEX concept. An ρ-VEX processor must be dynamically (runtime) reconfigurable to behave as a single large processor, two medium-sized processors, or four small processors. This allows a scheduler to optimize for energy and/or performance...
student report 2016