Searched for: subject%3A%22%25CF%2581%255C-VEX%22
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Verrer, Daan (author)
Modern implementations of encryption algorithms on CPU’s that use frequent memory lookups of precomputed functions, are vulnerable to Cache based Side­Channel Attacks. The ρ­-VEX processor, a runtime reconfigurable VLIW processor developed at the Computer and Quantum Engineering department at the TU Delft was identified to possibly allow for...
master thesis 2021
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Vermaat, Bas (author)
The ρ-VEX is a processor designed at the Computer Engineering lab at TU Delft to be reconfigurable at runtime, resulting in a processor that can combine or separate instruction lanes according to the program requirements. The current cache for the ρ-VEX processor is direct mapped and always identical to the instruction group configuration. This...
master thesis 2021
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Ntasios, Angelos (author)
The last years, there has been a increasing trend in embedded system and FPGA im-plementations for greater flexibility and also, a rising adaptation of heterogeneous plat-forms. These platforms often include FPGAs and embedded cores side by side.ρ-VEXcore, developed and maintained by the Computer Engineering group of TU Delft, is aVLIW processor...
master thesis 2019
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Yanik, K.I.M. (author)
The trend of increasing performance by parallelism is followed by the adoption of heterogeneous systems. In order to allow more fine-tuned balancing between used thread- and instruction level parallelism, the heterogeneous ρ-VEX platform was developed. Pipelining has been a part of microprocessor development for decades to increase throughput of...
master thesis 2016
Searched for: subject%3A%22%25CF%2581%255C-VEX%22
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