Design and Automated Implementation of a DfT Architecture for 3D-SICs

Three-dimensional stacked integrated circuits (3D-SICs) implemented with through silicon vias (TSVs) and micro-bumps open new horizons for faster, smaller and more energy-efficient chips. As all microelectronic structures, these 3D chips and their interconnects need to be tested for manufacturing defects. This thesis was executed in the context...

On 3D Stacked IC Yield Improvement and 3D-DfT Test Architecture

Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) is an emerging technology. It provides heterogeneous integration, higher performance and bandwidth, and lower power consumption. However, 3D-SICs suffer from lower compound yield, especially those based on Wafer-to-Wafer (W2W) stacking. In addition, testability of such...

A Methodology for Early Exploration of TSV Interconnects in 3D Stacked ICs

Planar scaling of semiconductor ICs for achieving higher integration seems to be on the brink of saturation. As an alternative solution, three-dimensional (3D) integration follows a more than Moore strategy in which circuit layers are stacked vertically. Although, 3D integration technology has moved from Lab to Fab, a complete supply chain is...

3D Architecture Exploration for Multimedia Applications

Three-Dimensional (3D) silicon integration is an emerging technology that vertically stacks multiple silicon circuit layers. It enables a single chip to be divided over multiple layers, which are stacked on top of each other. A literature study is performed for this thesis, which presents the basic manufacturing techniques for this emerging...