Towards a Scalable Sun Position Sensor with Monolithic Integration of the 3d Optics for Miniaturized Satellite Attitude Control

In this paper we present a sun position sensor platform with a scalable approach for the 3D integration of the sensor optics. This would facilitate the sun position sensor miniaturization, reduces fabrication cost and mitigates the need for sensor calibration. The sun position sensor platform is implemented in a seven mask BICMOS technology with...

Through Package Via: A bottom-up approach

The rapid development of semiconductor industry in the past decades has reshaped the world tremendously and greatly changed people's lives. Two-dimensional (2D) down-sizing of semiconductor devices following the “Moore's law” for many years is now reaching its boundary conditions of further exponential growth and three-dimensional (3D)...

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their...

The direct growth of carbon nanotubes as vertical interconnects in 3D integrated circuits

Carbon nanotubes (CNT) have been proposed for many applications in integrated circuits (IC): ranging from transistors and interconnects to sensors and actuators. For these applications it is crucial to integrate CNT directly alongside electronics, something which has not been achieved before. In this work we demonstrate the direct growth of CNT...

Thermal-Aware Design and Runtime Management of 3D Stacked Multiprocessors

The sustained increase in computational performance demanded by next-generation applications drives the increasing core counts of modern multiprocessor systems. However, in the dark silicon era, the performance levels and integration density of such systems is limited by thermal constraints of their physical package. These constraints are more...

High aspect-ratio MEMS devices for the next generation of THz/MHz passive components

The realization of efficient passive devices directly on chip represents one of the most intriguing challenges in IC fabrication processes. The performance of such devices are intrinsically determined by physical parameters that cannot be easily scaled, making the on-chip integration of such components a complex task to solve. To pursue the...

Carbon Nanotubes as Vertical Interconnects in 3D Integrated Circuits

Interconnects in integrated circuits (IC) are the major cause of power dissipation and delay. 3D integration has been proposed as a method to reduce these issues. For this 3D integration, fabrication of high aspect ratio reliable vertical interconnects (vias) are required. For this new materials, like carbon nanotubes (CNT), are being considered...

Design and Automated Implementation of a DfT Architecture for 3D-SICs

Three-dimensional stacked integrated circuits (3D-SICs) implemented with through silicon vias (TSVs) and micro-bumps open new horizons for faster, smaller and more energy-efficient chips. As all microelectronic structures, these 3D chips and their interconnects need to be tested for manufacturing defects. This thesis was executed in the context...

Carbon nanotubes as vertical interconnects in 3D integrated circuits

In integrated circuits the delay caused by interconnects, their power consumption, production and reliability are challenges to be solved. Using the third dimension for additional layers of transistor has been proposed as a solution to this problem by reducing the length of the interconnects. A problem in 3D integration is the creation of...