Yield and Cost Analysis or 3D Stacked ICs

3D stacking is an emerging technology promising many benefits such as low latency between stacked dies, reduced power consumption, high bandwidth communication, improved form factor and package volume density, heterogeneous integration, and low-cost manufacturing. However, it requires modification of existing methods and/or introduction of new...

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and...

A DfT architecture for 3D-SICs based on a standardizable die wrapper

Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows prebond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular...