High-speed Data Acquisition and Processing for Transcranial Functional Ultrasound Brain Imaging

Functional ultrasound is by now a well-established technique in the neuroscience community to measure brain activity. However, the transcranial application of functional ultrasound on humans, with the exception of the acoustic windows in the skull, remains a huge challenge because of the properties of the cranial bone the acoustic waves will...

Optimizing Memory Mapping for Dataflow Inference Accelerators: Efficient Memory Utilization on FPGAs

Convolutional Neural Network (CNN) inference has gained a significant amount of traction for performing tasks like speech recognition and image classification. To improve the accuracy with which these tasks can be performed, CNNs are typically designed to be deep, encompassing a large number of neural network layers. As a result, the...

VHDL Implementation of 4096-bit RNS Montgomery Modular Exponentiation for RSA Encryption

Modular exponentiation is the basis needed to perform RSA encryption and decryption. Execution of 4096-bit modular exponentiation using an embedded system requires many arithmetic operations. This work aims to improve the performance of modular exponentiation for an existing FPGA platform containing a soft core RISC-V processor. The solution is...

Hala ρ-VEX: Highly-Programmable Dynamically-Reconfigurable FPGA-based Streaming Platform for Image Processing

Image processing is found in many fields and in many domains. Advances in<br/>digital image capturing technology allows for faster video rates, of higher quality, than has been seen before and that trend continues. With greater resolution and increased data flow there is also a need for faster and better hardware for image processing. As the...

A fault tolerant memory architecture for a RISC-V softcore

Technolution B.V. is developing a custom Reduced Instruction Set Computer (RISC)-V based softcore for implementation on a Field Programmable Gate Array (FPGA). Previously, the softcore used the memory residing on the FPGA only, which is very limited in capacity and limits scaling. To solve this problem, a connection is made from the softcore to...

Hardware Components for Real-Time Stereo Matching: Acceleration of 3D HD TV with FPGAs

In recent 3D TV market, the technologies addressing to the applications such as stereoscopic depth scaling, glass-free 3D display, and Free Viewpoint TV are getting more attentions. A low-cost solution that can synthesize intermediate views from stereoscopic input contents(left and right camera views) is strongly needed. To render the...