Off-chip Self-timed SNN Custom Digital Interconnect System

To support the spike propagates between neurons, neuromorphic computing systems always require a high-speed communication link. <br/>Meanwhile, spiking neural networks are event-driven so that the communication links normally exclude the clock signal and related blocks. This thesis aims to develop a self-timed off-chip interconnect system with...

Designing Asynchronous Gate Library with new System Level Trade-offs

This dissertation describes an approach to building a self-timed asynchronous pulse-mode serial link circuit. Unlike asynchronous handshake circuits or synchronous circuits, this design style does not require any feedback control blocks, which can increase latency, or any clock recovery circuits, which can increase energy consumption and...