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Bolatkale, M. (author), Breems, LJ (author), Rutten, Robert (author), Makinwa, K.A.A. (author)
A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while...
journal article 2011