Expressing Intent: An evaluation of the Arm Machine Readable Specification

The behaviour of software is intrinsically linked to the hardware it runs on. As hardware innovations continuously change the landscape of computing, software has to adapt to these changes. Running legacy software on new hardware requires either the old hardware to be emulated, or a very time-consuming and error-prone process of reverse...

Lasagne: a static binary translator for weak memory model architectures

The emergence of new architectures create a recurring challenge to ensure that existing programs still work on them. Manually porting legacy code is often impractical. Static binary translation (SBT) is a process where a program's binary is automatically translated from one architecture to another, while preserving their original semantics....

Risotto: A Dynamic Binary Translator for Weak Memory Model Architectures

Dynamic Binary Translation (DBT) is a powerful approach to support cross-architecture emulation of unmodified binaries. However, DBT systems face correctness and performance challenges, when emulating concurrent binaries from strong to weak memory consistency architectures. As a matter of fact, we report several translation errors in QEMU,...

Dynamic Hardware Binary Translator for ρ-VEX

The last years, there has been a increasing trend in embedded system and FPGA im-plementations for greater flexibility and also, a rising adaptation of heterogeneous plat-forms. These platforms often include FPGAs and embedded cores side by side.ρ-VEXcore, developed and maintained by the Computer Engineering group of TU Delft, is aVLIW processor...