Zero-serialization, Zero-copy memory pooling in compute clusters: Disaggregated memory made accessible

With the rise of the new interconnect standards CXL and previously OpenCAPI, has come a great deal of possibilities to step away from the classical approach where CPUs are in charge of moving data between external devices and local memory. Specifically, OpenCAPI allows for attached devices to directly interface with the host memory bus in a near...

Neural network partitioning for resource-limited environments

The demand for implementing neural networks on edge devices has rapidly increased as they allow designers to move away from expensive server-grade hardware. However, due to the limited resources available on edge devices, it is challenging to implement complex neural networks. This study selected the Kria SoM KV260 hardware platform due to its...

Implementation and Evaluation of Packed-SIMD Instructions for a RISC-V Processor

With the increase in the amount of data being gathered, the need for data processing is also rising. Furthermore, in addition to the proprietary ISAs that have been prevalent, the free and open RISC-V ISA has seen major interest. The modularity of the RISC-V ISA allows it to be extended with many instruction set extensions. One such extension...

OpenACC GPU implementation of double-stage delay-multiply-and-sum algorithm: Toward enhanced real-time linear-array photoacoustic tomography

Double-stage delay-multiply-and-sum (DS-DMAS) is one of the algorithms proposed for photoacoustic image reconstruction where a linear-array transducer is used to detect signals. This algorithm provides a higher contrast image in comparison with the conventional delay-multiply-and-sum (DMAS) and delay-and-sum (DAS), but it imposes a high...

Passive Cooling of mm-Wave Active Integrated 5G Base Station Antennas Using CPU Heatsinks

The challenge of cooling in mm-wave chipintegrated base station antenna arrays is addressed. Several approaches in thermal modeling of electronics are revisited and discussed. The two-resistor compact thermal model is applied to predict the junction temperatures of the beamformer chips. Thermal simulations are performed for two fabricated arrays...

GPU-accelerated Double-Stage Delay-Multiply-and-Sum Algorithm for Fast Photoacoustic Tomography Using LED Excitation and Linear Arrays

Double-stage delay-multiply-and-sum (DS-DMAS) is an algorithm proposed for photoacoustic image reconstruction. The DS-DMAS algorithm offers a higher contrast than conventional delay-and-sum and delay-multiply and-sum but at the expense of higher computational complexity. Here, we utilized a compute unified device architecture (CUDA) graphics...

Reduction of Computing Time for Numerical Pricing of European Multi-dimensional Options based on the COS Method

Numerical integration methods such as the Fourier-based COS method can be used for effciently and accurately pricing financial products. The COS method can be applied to options on one underlying stock as well as on multiple underlying stocks. However, this method suffers from an exponential increase in computational complexity as the dimensions...

Efficient High Performance Computing on Heterogeneous Platforms

Heterogeneous platforms are mixes of different processing units in a compute node (e.g., CPUs+GPUs, CPU+MICs) or a chip package (e.g., APUs). This type of platforms keeps gaining popularity in various computer systems ranging from supercomputers to mobile devices. In this context, improving their efficiency and usability has become increasingly...

Performance Improvement of Optical Algorithms on Multicore Platforms

ASML is one of the world's largest suppliers of lithography systems for the semiconductor industry. ASML designs and develops machines that are used to print circuits on silicon wafers, to produce IC chips. These circuits have to be printed with accuracy of up to 2nm. For this purpose, the machines incorporate several measurement systems. The...

3D Architecture Exploration for Multimedia Applications

Three-Dimensional (3D) silicon integration is an emerging technology that vertically stacks multiple silicon circuit layers. It enables a single chip to be divided over multiple layers, which are stacked on top of each other. A literature study is performed for this thesis, which presents the basic manufacturing techniques for this emerging...

Development of a workload set for multi-core architectures

With the rise of multi-core chips in commodity hardware, the need for specialized workloads to evaluate the performance of multi-core systems has become apparent. The current generation of workloads used for evaluating multi-core systems often consist of sequential programs not capable of running on multiple processors and are therefore of...