A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <-54-dBc Spurs Under 50-mV _ppSupply Ripple

In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the...

A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications

This article presents a 4-to-5GHz LC oscillator operating at 4.2K for quantum computing applications. The phase noise (PN) specification of the oscillator is derived based on the control fidelity for a single-qubit operation. To reveal the substantial gap between the theoretical predictions and measurement results at cryogenic temperatures, a...

A numerical Bayesian-calibrated characterization method for multiscale prepreg preforming simulations with tension-shear coupling

Carbon fiber reinforced plastics (CFRPs) are attracting growing attention in industry because of their enhanced properties. Preforming of thermoset carbon fiber prepregs is one of the most common production techniques of CFRPs. To simulate preforming, several computational methods have been developed. Most of these methods, however, obtain...

A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation

In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it may directly operate from a switched-mode dc-dc converter generating fairly large ripples. A ripple replication block (RRB) generates an amplified ripple replica at the gate terminal of the tail current source to stabilize the oscillator's tail...

An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop

To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order &amp;#x0394;&amp;#x03A3; time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A...