Searched for: subject%3A%22Digital%255C+control%22
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Gürleyük, C. (author), Pan, S. (author), Makinwa, K.A.A. (author)
This article presents a 16-MHz RC frequency reference implemented in a standard 180-nm CMOS process. It consists of a frequency-locked loop (FLL) in which the output frequency of a digitally controlled oscillator (DCO) is locked to the frequency-phase characteristic of a Wien bridge RC filter. Since it is made from on-chip resistors and...
journal article 2022
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Pimenta, Matheus (author), Gürleyük, C. (author), Walsh, Paul (author), O’Keeffe, Daniel (author), Babaie, M. (author), Makinwa, K.A.A. (author)
This article presents a low-power eddy-current sensor interface for touch applications. It is based on a bang-bang digital phase-locked loop (DPLL) that converts the displacement of a metal target into digital information. The PLL consists of a digitally controlled oscillator (DCO) built around a sensing coil and a capacitive DAC, a...
journal article 2021
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Riekerk, Calvin (author)
Wireless power transfer (WPT) is becoming a popular choice for charging of batteries in various applications. Particularly, the increase in popularity of electrical vehicles (EVs) and the pursuit of user convenience for charging the batteries makes WPT an attractive solution. The usage of WPT in e-transportation is not straightforward because...
master thesis 2020
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de Albuquerque Gleizer, G. (author), Mazo, M. (author)
Self-triggered control (STC) and periodic event-triggered control (PETC) are aperiodic sampling techniques aiming at reducing control data communication when compared to periodic sampling. In both techniques, the effects of measurement noise in continuous-time systems with output feedback are unaddressed. In this work we prove that additive...
journal article 2020
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de Albuquerque Gleizer, G. (author), Mazo, M. (author)
This paper addresses the problem of modeling and scheduling the transmissions generated by multiple event-triggered control (ETC) loops sharing a network. We present a method to build a finite-state similar model of the traffic generated by periodic ETC (PETC), which by construction mitigates the combinatorial explosion that is typical of...
journal article 2020
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Rebers, Marjolein (author), Breysens, G. (author)
The goal of this bachelor thesis is to develop a control system that controls the temperature of a microthruster. This system also needs to acquire data for research. The microthruster contains a resistor that is used both as a heater and as a sensor. To facilitate the acquisition of data and the testing of the control system, a lab setup with a...
bachelor thesis 2019
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Chen, Y. (author), Liu, Yao-Hong (author), Zong, Z. (author), Dijkhuis, Johan (author), Dolmans, Guido (author), Staszewski, R.B. (author), Babaie, M. (author)
In this paper, we propose a method to suppress supply pushing of an LC oscillator such that it may directly operate from a switched-mode dc-dc converter generating fairly large ripples. A ripple replication block (RRB) generates an amplified ripple replica at the gate terminal of the tail current source to stabilize the oscillator's tail...
journal article 2019
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Zong, Z. (author), Chen, Peng (author), Staszewski, R.B. (author)
In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f <sup>3</sup> ) and thermal (1/f <sup>2</sup> ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong...
journal article 2019
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Pourmousavian, Naser (author), Kuo, Feng Wei (author), Siriburanon, Teerachot (author), Babaie, M. (author), Staszewski, R.B. (author)
This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter ``doubles'' the supply voltage to all the digital circuitry and particularly regulates the time-to...
journal article 2018
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Gürleyük, C. (author), Pedala', L. (author), Pan, S. (author), Makinwa, K.A.A. (author), Sebastiano, F. (author)
This paper presents a 7-MHz CMOS RC frequency reference. It consists of a frequency-locked loop in which the output frequency of a digitally controlled oscillator (DCO) is locked to the combined phase shifts of two independent RC (Wien bridge) filters, each employing resistors with complementary temperature coefficients. The filters are driven...
journal article 2018
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Kuo, Feng-Wei (author), Babaie, M. (author), Chen, Huan-Neng (Ron) (author), Cho, Lan-Chou (author), Jou, Chewn-Pu (author), Chen, Mark (author), Staszewski, R.B. (author)
We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal...
journal article 2018
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de Albuquerque Gleizer, G. (author), Mazo, M. (author)
In this work we propose a Self-Triggered Control (STC) strategy for linear time-invariant (LTI) systems subject to bounded disturbances, using LTI discrete-time dynamic output-feedback. The STC logic computes worst-case triggering times from available information, based on a Periodic Event Triggered Control (PETC) triggering function. In the...
journal article 2018
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Ronchini Ximenes, A. (author), Vlachogiannakis, G. (author), Staszewski, R.B. (author)
In this paper, we apply various area reduction techniques on an inductor–capacitor (LC)-tank oscillator in order to make its size comparable to that of ring oscillators (ROs), while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The resulting oscillator employs a proposed ultracompact...
journal article 2017
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Kuo, Feng-Wei (author), Binsfeld Ferreira, S. (author), Chen, Huan-Neng Ron (author), Cho, Lan-Chou (author), Jou, Chewn-Pu (author), Hsueh, Fu-Lung (author), Madadi, I. (author), Tohidian, M. (author), Shahmohammadi, M. (author), Babaie, M. (author), Staszewski, R.B. (author)
We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F<sub>2</sub>...
journal article 2017
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Bashir, I. (author), Staszewski, R.B. (author), Balsara, Poras T. (author)
We present a numerical model of a wideband injection-locked frequency modulator used in a polar transmitter for 3G cellular radio application. At the heart of the system is a self-injection-locked oscillator with a programmable linear tuning range of up to 200 MHz at 4-GHz oscillation frequency. The oscillator is injection locked to a time...
journal article 2017
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Zhou, L. (author)
master thesis 2016
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Babaie, M. (author), Kuo, F (author), Chen, H (author), Cho, L (author), Jou, C. P. (author), Hsueh, F. L. (author), Shahmohammadi, M. (author), Staszewski, R.B. (author)
We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup...
journal article 2016
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Shahmohammadi, M. (author), Babaie, M. (author), Staszewski, R.B. (author)
In this paper, we propose a method to reduce a flicker (1/f) noise upconversion in voltage-biased RF oscillators. Excited by a harmonically rich tank current, a typical oscillation voltage waveform is observed to have asymmetric rise and fall times due to even-order current harmonics flowing into the capacitive part, as it presents the lowest...
journal article 2016
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Ahmadi Mehr, S.A.R. (author), Tohidian, M. (author), Staszeski, R.B. (author)
In modern RF system on chips (SoCs), the digital content consumes up to 85% of the IC chip area. The recent push to integrate multiple RF-SoC cores is met with heavy resistance by the remaining RF/analog circuitry, which creates numerous strong aggressors and weak victims leading to RF performance degradation. A key such mechanism is injection...
journal article 2015
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Zhuang, J. (author), Staszewski, R.B. (author)
This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The natural predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing...
journal article 2014
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