Neural-Network Decoders for Quantum Error Correction Using Surface Codes: A Space Exploration of the Hardware Cost-Performance Tradeoffs

Quantum error correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their...

Cerebron: A Reconfigurable Architecture for Spatio-Temporal Sparse Spiking Neural Networks

Spiking neural networks (SNNs) are promising alternatives to artificial neural networks (ANNs) since they are more realistic brain-inspired computing models. SNNs have sparse neuron firing over time, i.e., spatiotemporal sparsity; thus, they are helpful in enabling energy-efficient hardware inference. However, exploiting the spatiotemporal...

Towards a Full-Flexible and Fast-Prototyping TOF-PET Block Detector Based on TDC-on-FPGA

Typically, a time-of-flight (TOF) PET block detector is built using application-specific integrated circuits (ASICs), since they integrate a high number of channels at a reasonable power consumption and into a small area. However, ASICs’ flexibility is limited and prototyping times are long because a semiconductor fabrication process is required...

Design of a Portable and Customizable Microprocessor for Rapid System Prototyping

Due to the increasing number of processors which are integrated in System On Chips (SOCs) the need for robust, highly configurable processors emerged. Preliminary research showed that commercial processors are not suited for many research projects due to the fact that they are closed source and they can not be modified. Open source processors on...