Hardware acceleration of artificial X-ray image generation

X-ray imaging systems play an important role in the diagnostic process of various medical conditions. Generating an accurate artificial X-ray image has multiple advantages. It allows for flexible configurations during generation. The resulting images can reduce testing time and cost, help the training of surgeons, and increase the amount of data...

Low-cost multi-core on-chip learning schemes

Nowadays, to reduce the dependence of devices on cloud servers, machine learning workloads are required to process data on the edge. Furthermore, to improve adaptability to uncontrolled environments, there is a growing need for on-chip learning. Limitations in power and area for edge devices have increased interest in low-cost neural network...

Jumping Shift: A Logarithmic Quantization Method for Low-Power CNN Acceleration

Logarithmic quantization for Convolutional Neural Networks (CNN): a) fits well typical weights and activation distributions, and b) allows the replacement of the multiplication operation by a shift operation that can be implemented with fewer hardware resources. We propose a new quantization method named Jumping Log Quantization (JLQ). The key...

A New Logarithmic Quantization Technique and Corresponding Processing Element Design for CNN Accelerators

Convolutional Neural Networks (CNN) have become a popular solution for computer vision problems. However, due to the high data volumes and intensive computation involved in CNNs, deploying CNNs on low-power hardware systems is still challenging.<br/>The power consumption of CNNs can be prohibitive in the most common implementation platforms:...

Hardware Implementation of the NTRU Deterministic Public Key Encryption

The increasing advancements in quantum computing have led to an increasing danger for the cyberspace. The current cryptographic algorithms that are used to enable secure communication across insecure channels have the potential to be brute-forced by sufficiently powerful quantum computers, endangering the security of many electronic devices and...

Analysis of Cache Attacks and Countermeasures on the ρ-­VEX Processor

Modern implementations of encryption algorithms on CPU’s that use frequent memory lookups of precomputed functions, are vulnerable to Cache based Side­Channel Attacks. The ρ­-VEX processor, a runtime reconfigurable VLIW processor developed at the Computer and Quantum Engineering department at the TU Delft was identified to possibly allow for...

Integration of a convolutional neural network for speech-to-text recognition in an FPGA compiler flow

Deep Neural Network (DNNs) have increased significantly in size over the past decade. Partly due to this, the accuracy of DNNs in image classification and speech recognition tasks has increased as well. This enables a great potential for such models to be applied in real-world applications. However, due to their size, the compute and power...

Exploring the Limits of Query Pushdown for SQL Acceleration on FPGAs

There has been an increasing interest in moving computation closer to storage in recent years due to significant improvements in memory technology. FPGAs were proven to be an exciting candidate for accelerating database workloads since they provide an energy-efficient, reconfigurable and high-performance computation platform. Therefore, FPGAs...

Dataflow Hardware Design for Big Data Acceleration Using Typed Interfaces

Recent trends in large-scale computing demonstrate continuous growth in the need for raw processing performance. At the same time, the slowdown of vertical scaling pushes the industry towards more energy-efficient heterogeneous architectures. With the appearance of FPGAs in the cloud and data centers, a new architecture is offered for offloading...

VHDL Implementation of 4096-bit RNS Montgomery Modular Exponentiation for RSA Encryption

Modular exponentiation is the basis needed to perform RSA encryption and decryption. Execution of 4096-bit modular exponentiation using an embedded system requires many arithmetic operations. This work aims to improve the performance of modular exponentiation for an existing FPGA platform containing a soft core RISC-V processor. The solution is...

Dynamic Hardware Binary Translator for ρ-VEX

The last years, there has been a increasing trend in embedded system and FPGA im-plementations for greater flexibility and also, a rising adaptation of heterogeneous plat-forms. These platforms often include FPGAs and embedded cores side by side.ρ-VEXcore, developed and maintained by the Computer Engineering group of TU Delft, is aVLIW processor...

An FPGA-based Snappy Decompressor-Filter

New interfaces to interconnect CPUs and accelerators at memory-class bandwidth pose new opportunities and challenges for the design of accelerators. This thesis studies one such accelerator, a decompressor for Parquet files compressed with the Snappy library. Our design targets reconfigurable logic (FPGAs) attached via the open coherent...

Low-Cost Smith-Waterman Acceleration

Due to advancing technology, genetic sequencing has become cheaper over the years. This has caused the demand for computational power to grow even faster than Moore's law. To remedy this problem, we analyzed low-cost hardware solutions to parallelize the computational part of the genetic sequencing. We proposed a novel method for calculating the...

Feasibilty Analysis for Hardware Acceleration of Pattern Recognition Algorithms

This thesis presents a feasibility analysis for hardware acceleration of the pattern recognition algorithms used by the Media Knowledge Engineering department at the Delft University of Technology. The feasibility analysis is conducted on a number of different algorithm classes. The Parzen Window algorithm appeared to be the most suitable option...