A Methodology for Improving gXR5 Speed and Accuracy

Computer Architects often walk the tightrope between performance, power and area while designing modern day processors. This daunting task is made even more challenging by short Time-to-Market requirements set by the clients. In light of these challenges, architectural simulators provide a much needed tool for the architects to gauge the impact...

Preventing Soft Errors and Hardware Trojans in RISC-V Cores

Soft errors in embedded systems' memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundancy methods to ensure critical application dependability. Another rising concern in secure, critical space...

Is RISC-V ready for Space? A Security Perspective

Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and...

Hardware enforced fine grained data labeling on RISC-V using RUST

Software bugs in many different variants can potentially leak sensitive data to an attacker. Implementing a separation mechanism for security domains can prevent incorrect or malicious code to leak sensitive data from one security domain to another. This work presents a separation mechanism based on labeling security domains with a label in...

Dynamic Hardware Binary Translator for ρ-VEX

The last years, there has been a increasing trend in embedded system and FPGA im-plementations for greater flexibility and also, a rising adaptation of heterogeneous plat-forms. These platforms often include FPGAs and embedded cores side by side.ρ-VEXcore, developed and maintained by the Computer Engineering group of TU Delft, is aVLIW processor...