ρ-VEX ASIC: The Design of an ASIC for a Dynamically Reconfigurable VLIW Processor with 24-port Register File

The ρ-VEX is a runtime reconfigurable VLIW processor. It is able to exploit both ILP as well as TLP by running one program in multiple lanes, or several programs concurrently. To accurately quantify its performance compared to other processors, it is implemented as an IC.<br/>A fully automatic scripted flow is described, constructing an...

Source-Synchronous Interface with All-Digital Data Recovery: A Low-cost Efficient Design

This thesis proposes a low-cost high-efficiency source-synchronous interface for high-speed inter-chip communication. The interface is composed of LVDS transceivers as external I/O buffers, and an all-digital data recovery, which can calibrate the received data phase to be aligned to the 90^◦ phase of the received half-rate reference...

The design of a global shutter CMOS image sensor in 110nm technology

The goal of this work described in this thesis is to design a CMOS image sensor chip, implementing pixels with a 4.8?m pitch with a peripheral readout circuitry in a 110nm CMOS process. The architecture of the CMOS image sensor is presented, with a functional illustration for every block. The 8T global shutter pixel noise, circuit and layout are...