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Rajaraman, V. (author), Pakula, L.S. (author), Pham, H.T.M. (author), Sarro, P.M. (author), French, P.J. (author)
This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide variety of surface- and thin-SOI...
conference paper 2009