Robust Wafer-Level Thin-Film Encapsulation (Packaging) of Microstructures (MEMS) using Low Stress PECVD Silicon Carbide

This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide variety of surface- and thin-SOI...

SOI Digital Accelerometer Based on Pull-in Time Configuration

The operation principle, design, fabrication and measurement results of a quasi digital accelerometer fabricated on a thin silicon-on-insulator (SOI) substrate is presented. The accelerometer features quasi-digital output, therefore eliminating the need for analogue signal conditioning. The accelerometer can be directly interfaced to digital...

DRIE and Bonding Assisted Low Cost MEMS Processing of In-plane HAR Inertial Sensors

We present a simple, flexible and low cost MEMS fabrication process, developed using deep reactive ion etching (DRIE) and wafer bonding technologies, for manufacturing in-plane high aspect ratio (HAR) inertial sensors. Among examples, the design and fabrication results of a two axis inertial device are presented. Fabricated device thickness...