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Chen, Jianyu (author), Al-Ars, Z. (author), Hofstee, H.P. (author)
In this paper, we present the design in reconfigurable logic of a matrix multiplier for matrices of 32-bit posit numbers with es=2 [1]. Vector dot products are computed without intermediate rounding as suggested by the proposed posit standard to maximally retain precision. An initial implementation targets the CAPI 1.0 interface on the POWER8...
conference paper 2018