Searched for: subject%3A%22Mitigation%22
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Cem Gursoy, Cemil (author), Kraak, D.H.P. (author), Ahmed, Foisal (author), Taouil, M. (author), Jenihhin, Maksim (author), Hamdioui, S. (author)
Memory designs require timing margins to compensate for aging and fabrication process variations. With technology downscaling, aging mechanisms became more apparent, and larger margins are considered necessary. This, in return, means a larger area requirement and lower performance for the memory. Bias Temperature Instability (BTI) is one of the...
conference paper 2022
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Kraak, D.H.P. (author), Agbo, I.O. (author), Taouil, M. (author), Hamdioui, S. (author), Weckx, Pieter (author), Cosemans, Stefan (author), Catthoor, Francky (author)
Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper...
conference paper 2019
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Kraak, D.H.P. (author), Gürsoy, C.C. (author), Agbo, I.O. (author), Taouil, M. (author), Jenihhin, M. (author), Raik, J. (author), Hamdioui, S. (author)
Integrated circuits typically contain design margins to compensate for aging. As aging impact increases with technology scaling, bigger margins are necessary to achieve the desired reliability. However, these increased margins lead to a reduced performance and lower yield. Alternatively, mitigation schemes can be deployed to reduce the aging....
conference paper 2019