Searched for: subject%3A%22Network%255C+on%255C+Chip%22
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Li, Siyue (author), Zhou, Shize (author), Xue, Yongqi (author), Fan, Wenjie (author), Cheng, Tong (author), Ji, Jinlun (author), Dai, Chenyang (author), Song, Wenqing (author), Gao, C. (author)
Network-on-Chip (NoC) is a scalable on-chip communication architecture for the NN accelerator, but with the increase in the number of nodes, the communication delay becomes higher. Applications such as machine learning have a certain resilience to noisy/erroneous transmitted data. Therefore, approximate communication becomes a promising solution...
journal article 2024
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Zhou, Yongkang (author)
Spiking neural networks (SNN), as the third-generation artificial neural network, has a similar potential pulse triggering mechanism to the biological neuron. This mechanism enables the spiking neural network to increase computing power compared to the traditional artificial neural network to process complex information. However, a large number...
master thesis 2022
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Rodrigo, Santiago (author), Spanò, Domenico (author), Bandic, M. (author), Abadal, Sergi (author), van Someren, J. (author), Ovide, Anabel (author), Feld, S. (author), Almudéver, Carmen G. (author), Alarcón, Eduard (author)
Quantum many-core processors are envisioned as the ultimate solution for the scalability of quantum computers. Based upon Noisy Intermediate-Scale Quantum (NISQ) chips interconnected in a sort of quantum intranet, they enable large algorithms to be executed on current and close future technology. In order to optimize such architectures, it is...
conference paper 2022
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Reinbrecht, Cezar (author), Aljuffri, A.A.M. (author), Hamdioui, S. (author), Taouil, M. (author), Forlin, Bruno E. (author), Sepulveda, Johanna (author)
Multi-Processor System-on-Chips (MPSoCs) are popular computational platforms for a wide variety of applications due to their energy efficiency and flexibility. Like many other platforms they are vulnerable to Side Channel Attacks (SCAs). In particular, Logical SCAs (LSCAs) are very powerful as sensitive information can be retrieved by simply...
conference paper 2020
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Kumar, S.S. (author), Zjajo, Amir (author), van Leuken, T.G.R.M. (author)
In this paper, we present the Immediate Neighbourhood Temperature (INT) routing algorithm which balances thermal profiles across dynamically-throttled 3D NoCs by adaptively routing interconnect traffic based on runtime temperature monitoring. INT avoids the overheads of system-wide temperature monitoring by relying on the heat transfer...
journal article 2017
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Chen, C. (author), Fu, Yaowen (author), Cotofana, S.D. (author)
To maximize the utilization of the available networks-on-chip (NoCs) link bandwidth, partially faulty links with low fault level should be utilized while heavily defected (HD) links should be deactivated and dealt with by means of a fault tolerant routing algorithm. To reach this target, we make the following contributions in this paper: 1) we...
journal article 2017
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Kukreja, R.S. (author)
As technology is improving and the performance of a single core has reached its peak performance, Multicore Systems on Chip have emerged as the trend of System on Chip designs to meet the performance requirements of high throughput embedded applications. The communication infrastructure (interconnect) of such systems are as vital as its various...
master thesis 2015
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Kumar, S.S. (author)
The sustained increase in computational performance demanded by next-generation applications drives the increasing core counts of modern multiprocessor systems. However, in the dark silicon era, the performance levels and integration density of such systems is limited by thermal constraints of their physical package. These constraints are more...
doctoral thesis 2015
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Chen, C. (author)
The aggressive semiconductor technology scaling provides the means for doubling the amount of transistors on a single chip each and every 18 months. To efficiently utilize these vast chip resources, Multi-Processor Systems on Chip (MPSoCs) integrated with a Network-on-Chip (NoC) communication infrastructure have been widely investigated. However...
doctoral thesis 2015
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Wahlah, M.A. (author)
Technology down-scaling and platform-based designs have enforced a number of application and architecture trends for system-on-chip (SOC) designs. A modern SOC is now a multi-functional machine that can execute a large number of complex applications by using tens or even hundreds of intellectual properties (IPs). Meanwhile, due to a number of...
doctoral thesis 2012
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Ludovici, D. (author)
NoCs have been considered as the new design paradigm for large MPSoC systems in the past ten years. In the beginning NoCs were radically different compared to the current state of the art mainly due to the unexpected unique challenges that system designers had to solve with the evolving CMOS technology. In fact, various hidden physical level...
doctoral thesis 2011
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Van Kampenhout, J.R. (author)
In this thesis we consider the application of multi-cores in safety critical real-time systems, especially avionics. In our literature study we extract two major challenges. Firstly the unpredictability that comes from the concurrent access of shared resources (especially the on-chip interconnect) must be dealt with. To address this we propose...
master thesis 2011
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Verschoor, M. (author)
Interconnect centric security in multi core System-on-Chip (SoC) is an area of increasing concern. Monitoring and manipulation of the SoC interconnect yields great potential to bypass higher level security mechanisms. This thesis proposes SoC-TLS: a cryptographic hardware solution aimed to protect intra SoC communication against malicious IP and...
master thesis 2011
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Hur, J.Y. (author)
This thesis presents our investigations on how to efficiently utilize on-chip wires to improve network performance in reconfigurable hardware. A fieldprogrammable gate array (FPGA), as a key component in a modern reconfigurable platform, accommodates many-millions of wires and the on-demand reconfigurability is realized using this abundance of...
doctoral thesis 2011
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Escudero Martínez, M. (author)
Prototyping Systems on Chip (SoC) on FPGA technology improves the time that the de- signer needs to spend in the verification stage when developing new systems or upgrading the existing ones. However, FPGA prototyping is very challenging due to the few resources available in this chips, and often the large designs do not fit into one single FPGA...
master thesis 2010
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Kumar, S.S. (author)
With the performance of single-core processors approaching its limits, an increased amount of research effort is focused on chip multiprocessors (CMP). However, existing lock-based synchronization methods that are critical to performing parallel computation possess limited scalability and are inherently complex to use while programming. This...
master thesis 2010
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Van den Berg, A. (author), Ren, P. (author), Marinissen, E.J. (author), Gaydadjiev, G. (author), Goossens, K. (author)
Test data travels through a System on Chip (SOC) from the chip pins to the Core-Under-Test (CUT) and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented using dedicated communication infrastructure. However, also existing functional interconnect, such as a bus or Network on Chip (NOC), can be reused as TAM; this...
journal article 2010
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Karadeniz, T. (author)
High-performance routers have the task of transmitting traffic in between the nodes of the Internet, the network of networks that carries the vast amount of information among billions of users. The switch fabric is the key building block of every router, and various switch fabric architectures are used in the market products. The crossbar-based...
master thesis 2010
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De Windt, J. (author)
Bus based interconnects are commonly used to connect Intellectual Properties (IPs) on System-on-Chip (SoC). However, as the number of high performance IPs with large communication requirements in a Multi Processor SoC (MPSoC) increases, the bus interconnects become a communication bottleneck. To overcome this limitation, the bus based...
master thesis 2009
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Nazarian, G. (author)
Due to recent progress in semiconductor technology, communication is becoming the major source of expense in today's chip design. Network-on-Chip (NoC) is a new paradigm for solving the problem of complex communication on the chips. However, in order to NoC to be ecient in providing complex on-chip communication, the designers should be assured...
master thesis 2008
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