HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators

Modeling of router structure for SNN-applicable NoC definitions

Characterizing the spatio-temporal qubit traffic of a quantum intranet aiming at modular quantum computer architectures

Guard-NoC: A protection against side-channel attacks for MPSoCs

Immediate Neighbourhood Temperature Adaptive Routing for Dynamically Throttled 3-D Networks-on-Chip

Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links

Modeling and performance analysis of a high bandwidth, low power ring interconnect

Thermal-Aware Design and Runtime Management of 3D Stacked Multiprocessors

Towards Dependable Network-on-Chip Architectures

Field Programmable Gate Arrays with Hardwired Networks on Chip

Technology Aware Network-on-Chip Connectivity and Synchronization Design

Deterministic Task Transfer in Network-on-Chip Based Multi-Core Processors

Design of a Crypto Core for Securing Intra System-on-Chip Communication

Customizing and hardwiring on-chip interconnects in FPGAs

An Off-Chip Bridge for On-Chip Network-Based Systems Supporting Traffic Quality of Service

TMFab: A Transactional Memory Fabric for Chip Multiprocessors

Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism

Hardware design and implementation of a network-on-chip based high performance crossbar switch Fabric

Protocol conversions for the Aethereal Networks-on-Chip

On-line testing of routers in networks-on-chip