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A Cryo-CMOS PLL for Quantum Computing Applications

Gong, J. (author), Charbon-Iwasaki-Charbon, E. (author), Sebastiano, F. (author), Babaie, M. (author)

This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit operation. By considering the benefits and challenges of cryogenic operation, a dedicated...

journal article 2023

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A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

Gao, Z. (author), He, J. (author), Fritz, Martin (author), Shen, Y. (author), Zong, Z. (author), Spalink, Gerd (author), Alavi, S.M. (author), Staszewski, R.B. (author), Babaie, M. (author)

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO)...

journal article 2023

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Charge-Sampling DTC based Fractional-N Phase-Locked Loop with Background DTC Gain Calibration

Gurbaxani, Rishabh (author)

Phase-locked loops (PLLs) are ubiquitous in many RF applications such as frequency synthesizers in wireline and wireless transceivers. In this project, a charge-sampling PLL has been designed, which employs a charge-domain sub-sampling phase detector. The high gain of the phase detector helps suppress the in-band phase noise, while the lowered...

master thesis 2022

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Guidelines for Stability Analysis of the DDSRF-PLL Using LTI and LTP Modelling in the Presence of Imbalance

Beloqui Larumbe, L. (author), Qin, Z. (author), Bauer, P. (author)

In this article, the Linear Time Invariant (LTI) and Linear Time Periodic (LTP) models of two different implementations of the DDSRF-PLL in the presence of voltage imbalance are derived analytically. The accuracy of the models is investigated with time domain simulations, frequency scans, and stability analysis. On top of this, a guideline for...

journal article 2022

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A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology

Wang, Zhongkai (author), Choi, Minsoo (author), Kwon, Paul (author), Lee, Kyoungtae (author), Yin, Bozhi (author), Liu, Zhaokai (author), Park, Kwanseo (author), Biswas, Ayan (author), Du, S. (author)

This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The...

conference paper 2022

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A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow

Wang, Zhongkai (author), Choi, Minsoo (author), Wright, John (author), Lee, Kyoungtae (author), Liu, Zhaokai (author), Yin, Bozhi (author), Han, Jaeduk (author), Du, S. (author), Alon, Elad (author)

We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The...

conference paper 2022

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A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications

Gong, J. (author), Chen, Y. (author), Charbon-Iwasaki-Charbon, E. (author), Sebastiano, F. (author), Babaie, M. (author)

This article presents a 4-to-5GHz LC oscillator operating at 4.2K for quantum computing applications. The phase noise (PN) specification of the oscillator is derived based on the control fidelity for a single-qubit operation. To reveal the substantial gap between the theoretical predictions and measurement results at cryogenic temperatures, a...

journal article 2022

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A novel frequency-tracking loop based on sub-Nyquist samplers for a wide locking range and fast locking

Sannidhanam, Praneetha (author)

With the emergence of new communication standards like Fifth-­Generation New Radio (5G NR), technologies are being developed to exploit millimeter­ wave (mm-­wave) frequency bands from 30­300 GHz, for their advantage of high bandwidth availability. Generation of carrier frequencies for these mm-­wave applications imposes a challenging...

master thesis 2021

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Impedance Modeling for Three-Phase Inverters with Double Synchronous Reference Frame Current Controller in the Presence of Imbalance

Beloqui Larumbe, L. (author), Qin, Z. (author), Wang, L. (author), Bauer, P. (author)

This article presents a small-signal model for power-electronics converters that use a typical control structure in wind energy applications: the double synchronous reference frame current control. The article considers the presence of unbalanced currents and voltages, and analyzes their impact on the frequency couplings of the converter. In...

journal article 2021

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A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration

Liu, Bangan (author), Zhang, Yuncheng (author), Qiu, Junjun (author), Ngo, Huy Cu (author), Deng, Wei (author), Nakata, Kengo (author), Yoshioka, Toru (author), Emmei, Jun (author), Pang, Jian (author), Someya, T. (author)

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To...

journal article 2021

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A 200-μW Interface for High-Resolution Eddy-Current Displacement Sensors

Pimenta, Matheus (author), Gürleyük, C. (author), Walsh, Paul (author), O’Keeffe, Daniel (author), Babaie, M. (author), Makinwa, K.A.A. (author)

This article presents a low-power eddy-current sensor interface for touch applications. It is based on a bang-bang digital phase-locked loop (DPLL) that converts the displacement of a metal target into digital information. The PLL consists of a digitally controlled oscillator (DCO) built around a sensing coil and a capacitive DAC, a...

journal article 2021

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A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

Gong, J. (author), Sebastiano, F. (author), Charbon-Iwasaki-Charbon, E. (author), Babaie, M. (author)

This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of-258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves-65 dBc of reference spur by both minimizing the modulated capacitance seen by the VCO tank and...

conference paper 2020

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A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS

Chen, Peng (author), Zhang, Feifei (author), Zong, Z. (author), Hu, Suoping (author), Siriburanon, Teerachot (author), Staszewski, R.B. (author)

This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold...

journal article 2019

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A PLL-based eddy current displacement sensor for button applications

Ferreira Pimenta, Matheus (author)

This thesis presents an Eddy current sensor (ECS) for button readout applications. By employing a Phase-locked loop to perform a frequency readout, it was possible to significantly reduce the power consumption of the interface while achieving resolutions comparable to prior arts making it a more suitable solution for portable applications. The...

master thesis 2019

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Control Challenges and Solutions for Power Factor Correction

Does, Luc (author)

In this thesis, the design and implementation of an improved current controller for grid-tied converters is discussed. Using this improved current controller, a power factor correction test platform achieves practically zero AC and DC error in steady-state. The power factor corrector accomplishes this by utilizing the parallel combination of a...

master thesis 2019

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A Low-Noise Fractional-N Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

Zong, Z. (author), Chen, Peng (author), Staszewski, R.B. (author)

In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f ³ ) and thermal (1/f ² ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong...

journal article 2019

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A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS

Pourmousavian, Naser (author), Kuo, Feng Wei (author), Siriburanon, Teerachot (author), Babaie, M. (author), Staszewski, R.B. (author)

This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5-V supply. While its digitally controlled oscillator (DCO) runs directly at 0.5 V, an internal switched-capacitor dc-dc converter ``doubles'' the supply voltage to all the digital circuitry and particularly regulates the time-to...

journal article 2018

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An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs

Kuo, Feng-Wei (author), Babaie, M. (author), Chen, Huan-Neng (Ron) (author), Cho, Lan-Chou (author), Jou, Chewn-Pu (author), Chen, Mark (author), Staszewski, R.B. (author)

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal...

journal article 2018

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An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop

Chen, Peng (author), Huang, Xiongchuan (author), Chen, Y. (author), Wu, Lianbo (author), Staszewski, R.B. (author)

To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order ΔΣ time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A...

journal article 2018

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A Bluetooth Low-Energy Transceiver with 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network

Kuo, Feng-Wei (author), Binsfeld Ferreira, S. (author), Chen, Huan-Neng Ron (author), Cho, Lan-Chou (author), Jou, Chewn-Pu (author), Hsueh, Fu-Lung (author), Madadi, I. (author), Tohidian, M. (author), Shahmohammadi, M. (author), Babaie, M. (author), Staszewski, R.B. (author)

We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital phase-locked loop (ADPLL) with a switched current-source digitally controlled oscillator (DCO) featuring low frequency pushing, and class-E/F₂...

journal article 2017