Searched for: subject%3A%22Pipeline%255C%2BADC%22
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Akter, M.S. (author)
This work mainly focuses on designing a low-power class-AB residue amplifier for a 12bit 500MS/sec pipeline ADC with digital calibration. A foreground ideal calibration test bench has been implemented in MATLAB to correct non-linearities of the amplifier up to the 5th order. A detailed comparison has been made between a class-A amplifier and a...
master thesis 2012
Sehgal, R. (author)
"Split-ADC" calibration is a recently proposed digital background calibration architecture. It requires a much lower number of cycles to calibrate the ADC errors due to its deterministic nature, without placing any additional analog complexity. While new error estimation techniques are being explored using this architecture through simulations,...
master thesis 2010
Wang, J. (author)
a 4-bit 250MHz sampling rate pipelined A/D converter, with 1.5-bit resolution per stage, has been designed by Cadence using TSMC 0.13um CMOS process. The ADC which works at 1.2 V supply voltage dissipates 15.23 mW and has an ENOB of 3.7 bits @ 100MHz sampling condition. The maximum DNL is 0.38 LSB, and the maximum INL is 0.352 LSB
master thesis 2009