Searched for: subject%3A%22Reconfigurable%255C+Computing%22
(1 - 15 of 15)
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Jaspers, M.J. (author)
With the advent of Next Generation Sequencing (NGS), the cost of sequencing human DNA has decreased significantly over the past decade. This decrease in cost has attracted a great deal of attention from medical research and is now transitioning to clinical practice. Precision medicine, tailored to a persons's genetic profile, is becoming a...
master thesis 2015
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Nadeem, M.F. (author)
In this dissertation, we propose the design of a simulation framework to investigate the performance of reconfigurable processors in distributed systems. The framework incorporates the partial reconfigurable functionality of the reconfigurable nodes. Depending on the available reconfigurable area, each node is able to execute more than one task...
doctoral thesis 2013
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Meeuws, R.J. (author)
Hardware estimation is an important factor in Hardware/Software Co-design. In this dissertation, we present the Quipu Modeling Approach, a high-level quantitative prediction model for HW/SW Partitioning using statistical methods. Our approach uses linear regression between software complexity metrics and hardware characteristics. The resulting...
doctoral thesis 2012
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Viswanathan, V. (author)
Dynamically reconfigurable architectures have demonstrated superior performance in comparison to the general-purpose processors. This thesis describes a generic approach for Dynamic Partial Reconfiguration (DPR) of a reconfigurable platform, connected to a general purpose system through a high-speed interconnect. Thus, the system can dynamically...
master thesis 2011
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Khizakanchery Natarajan, S.N. (author)
Recent developments in the Dynamic and Partial Reconfigurable Computing requires the presence of Operating System (OS) services like scheduler, placer, reconfiguration manager etc to manage the run-time activities in the reconfigurable resource. In this thesis, we address the Inter-Task communication, which is one of the OS services required to...
master thesis 2011
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Marconi, T. (author)
Runtime reconfigurable systems built upon devices with partial reconfiguration can provide reduction in overall hardware area, power efficiency, and economic cost in addition to the performance improvements due to better customization. However, the users of such systems have to be able to afford some additional costs compared to hardwired...
doctoral thesis 2011
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Dragomir, O.S. (author)
The focus of this dissertation is on kernel loops (K-loops), which are loop nests that contain hardware mapped kernels in the loop body. In this thesis, we propose methods for improving the performance of such K-loops, by using standard loop transformations for exposing and exploiting the coarse grain loop level parallelism. We target a...
doctoral thesis 2011
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Nawaz, Z.N. (author)
Reconfigurable computing, in which general purpose processor (GPP) is augmented with one or more FPGAs, is increasingly used for high-performance computing where massive fine-grain parallelism and pipelining can be exploited. A challenge is to exploit such massive parallelism on FPGAs and more specifically how to map an application on the...
doctoral thesis 2011
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Corina, M. (author)
master thesis 2010
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Fazlali, M. (author), Zakerolhosseini, A. (author), Gaydadjiev, G. (author)
High latencies in FPGA reconfiguration are known as a major overhead in run-time reconfigurable systems. This overhead can be reduced by merging multiple data flow graphs representing different kernels of the original program into a single (merged) datapath that will be configured less often compared to the separate datapaths scenario. However,...
journal article 2010
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Kachris, C. (author)
This dissertation presents our investigation on how to efficiently exploit reconfigurable hardware to design flexible, high performance, and power efficient network devices capable to adapt to varying processing requirements of network applications and traffic. The proposed reconfigurable network processing platform targets mainly access, edge,...
doctoral thesis 2007
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Calderon Rocabado, D.R.H. (author)
In this dissertation, we address the design of multi-functional arithmetic units working with the most common fixed-point number representations, namely: unsigned, sign-magnitude, fractional, ten's and two's complement notations. The main design goal is to collapse multiple complex arithmetic operations into a single, universal arithmetic unit,...
doctoral thesis 2007
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Sourdis, I. (author), Pnevmatikatos, D.N. (author), Vassiliadis, S. (author)
In this paper, we consider hardware-based scanning and analyzing packets payload in order to detect hazardous contents.We present two pattern matching techniques to compare incoming packets against intrusion detection search patterns. The first approach, decoded partial CAM (DpCAM), predecodes incoming characters, aligns the decoded data, and...
journal article 2007
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Meeuws, R.J. (author)
Heterogeneous System Development needs Hardware/Software Partitioning performed early on in the development process. In order to do this early on predictions of hardware resource usage and delay are necessary. In this thesis a Quantitative Model is presented that can make early predictions to support the partitioning process. The model is based...
master thesis 2007
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Kuzmanov, G.K. (author)
In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The proposed media Molen prototype is implemented on...
doctoral thesis 2004
Searched for: subject%3A%22Reconfigurable%255C+Computing%22
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