A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <-54-dBc Spurs Under 50-mV _ppSupply Ripple

In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the...

A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators

In this paper, we propose a method to reduce a flicker (1/f) noise upconversion in voltage-biased RF oscillators. Excited by a harmonically rich tank current, a typical oscillation voltage waveform is observed to have asymmetric rise and fall times due to even-order current harmonics flowing into the capacitive part, as it presents the lowest...

A Class-F CMOS Oscillator

An oscillator topology demonstrating an improved phase noise performance is proposed in this paper. It exploits the time-variant phase noise model with insights into the phase noise conversion mechanisms. The proposed oscillator is based on enforcing a pseudo-square voltage waveform around the LC tank by increasing the third-harmonic of the...