Calibration Techniques for Power-efficient Residue Amplifiers in Pipelined ADCs

Residue amplification plays a key role in determining the energy efficiency, area and performance of high-speed pipelined ADCs. At its core, a residue amplifier simply consists of four transistors that transfer a differential input voltage to a capacitive load with the desired gain. However, in order to ensure gain accuracy over PVT, the core...

A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier

This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push-pull structure with a ``split-capacitor'' biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so incomplete settling can be used to save power while still...

A 12-bit 500MS/s Pipeline Split-ADC

"Split-ADC" calibration is a recently proposed digital background calibration architecture. It requires a much lower number of cycles to calibrate the ADC errors due to its deterministic nature, without placing any additional analog complexity. While new error estimation techniques are being explored using this architecture through simulations,...