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Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs

Yuan, S. (author), Zhang, Z. (author), Fieback, M. (author), Xun, H. (author), Marinissen, E. J. (author), Kar, G. S. (author), Rao, S. (author), Couet, S. (author), Taouil, M. (author), Hamdioui, S. (author)

The development of Spin-Transfer Torque Magnetic RAMs (STT-MRAMs) mass production requires high-quality test solutions. Accurate and appropriate fault modeling is crucial for the realization of such solutions. This paper targets fault modeling and test generation for all interconnect and contact defects in STT-MRAMs and shows that using the...

conference paper 2023

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Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs

Xun, H. (author), Fieback, M. (author), Yuan, S. (author), Zhang, Ziwei (author), Taouil, M. (author), Hamdioui, S. (author)

Resistive Random Access Memory (RRAM) is a potential technology to replace conventional memories by providing low power consumption and high-density storage. As various manufacturing vendors make significant efforts to push it to high-volume production and commercialization, high-quality and efficient test solutions are of great importance. This...

conference paper 2023

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Online Fault Detection and Diagnosis in RRAM

Fieback, M. (author), Bradarić, Filip (author), Taouil, M. (author), Hamdioui, S. (author)

Resistive Random Access Memory (RRAM, or ReRAM) is a promising memory technology to replace Flash because of its low power consumption, high storage density, and simple integration in existing IC production processes. This has motivated many companies to invest in this technology. However, RRAM manufacturing introduces new failure mechanisms and...

conference paper 2023

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Characterization and Test of Intermittent Over RESET in RRAMs

Xun, H. (author), Fieback, M. (author), Yuan, S. (author), Aziza, Hassen (author), Heidekamp, Mathijs (author), Copetti, Thiago (author), Poehls, Leticia Bolzani (author), Taouil, M. (author), Hamdioui, S. (author)

Resistive Random Access Memories (RRAMs) are being commercialized with significant investment from several semiconductor companies. In order to provide efficient and high-quality test solutions to push high-volume production, a comprehensive understanding of manufacturing defects is significantly required. This paper identifies and characterizes...

conference paper 2023

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Device Aware Diagnosis for Unique Defects in STT-MRAMs

Aouichi, A. (author), Yuan, S. (author), Fieback, M. (author), Rao, Siddharth (author), Kim, Woojin (author), Marinissen, Erik Jan (author), Couet, Sebastien (author), Taouil, M. (author), Hamdioui, S. (author)

Spin-Transfer Torque Magnetic RAMs (STT-MRAMs) are on their way to commercialization. However, obtaining high-quality test and diagnosis solutions for STT-MRAMs is challenging due to the existence of unique defects in Magnetic Tunneling Junctions (MTJs). Recently, the Device-Aware Test (DA-Test) method has been put forward as an effective...

conference paper 2023

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Device-Aware Test for Ion Depletion Defects in RRAMs

Xun, H. (author), Yuan, S. (author), Fieback, M. (author), Taouil, M. (author), Hamdioui, S. (author), Aziza, Hassen (author)

Many companies are heavily investing in the commercialization of Resistive Random Access Memories (RRAMs). This calls for a comprehensive understanding of manufacturing defects to develop efficient and high-quality test and diagnosis solutions to push high-volume production. This paper identifies and characterizes a new defect based on silicon...

conference paper 2023

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Defects, Fault Modeling, and Test Development Framework for RRAMs

Fieback, M. (author), Cardoso Medeiros, G. (author), Wu, L. (author), Aziza, Hassen (author), Bishnoi, R.K. (author), Taouil, M. (author), Hamdioui, S. (author)

Resistive RAM (RRAM) is a promising technology to replace traditional technologies such as Flash, because of its low energy consumption, CMOS compatibility, and high density. Many companies are prototyping this technology to validate its potential. Bringing this technology to the market requires high-quality tests to ensure customer...

journal article 2022

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Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs

Wu, L. (author), Rao, Siddharth (author), Taouil, M. (author), Marinissen, Erik Jan (author), Kar, Gouri Sankar (author), Hamdioui, S. (author)

The manufacturing process of STT-MRAM requires unique steps to fabricate and integrate magnetic tunnel junction (MTJ) devices which are data-storing elements. Thus, understanding the defects in MTJs and their faulty behaviors are paramount for developing high-quality test solutions. This article applies the advanced device-aware test to...

journal article 2022

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Structured Test Development Approach for Computation-in-Memory Architectures

Fieback, M. (author), Taouil, M. (author), Hamdioui, S. (author)

Testing of Computation-in-Memory (CIM) designs based on emerging non-volatile memory technologies, such as resistive RAM (RRAM), is fundamentally different from testing traditional memories. Such designs allow not only for data storage (i.e., memory configuration) but also for the execution of logical and arithmetic operations (i.e., computing...

conference paper 2022

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Hierarchical Memory Diagnosis

Cardoso Medeiros, G. (author), Fieback, M. (author), Gebregiorgis, A.B. (author), Taouil, M. (author), Poehls, L. B. (author), Hamdioui, S. (author)

High-quality memory diagnosis methodologies are critical enablers for scaled memory devices as they reduce time to market and provide valuable information regarding test escapes and customer returns. This paper presents an efficient Hierarchical Memory Diagnosis (HMD) approach that accurately diagnoses faults in the entire memory. Faults are...

conference paper 2022

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Hard-to-Detect Fault Analysis in FinFET SRAMs

Cardoso Medeiros, G. (author), Fieback, M. (author), Wu, L. (author), Taouil, M. (author), Bolzani Poehls, L. M. (author), Hamdioui, S. (author)

Manufacturing defects can cause hard-to-detect (HTD) faults in fin field-effect transistor (FinFET) static random access memories (SRAMs). Detection of these faults, such as random read outputs and out-of-spec parametric deviations, is essential when testing FinFET SRAMs. Undetected HTD faults result in test escapes, which lead to early in-field...

journal article 2021

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Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM

Wu, L. (author), Rao, Siddharth (author), Taouil, M. (author), Marinissen, Erik Jan (author), Kar, Gouri Sankar (author), Hamdioui, S. (author)

Understanding the defects in magnetic tunnel junctions (MTJs) and their faulty behaviors are paramount for developing high-quality tests for STT-MRAM. This paper characterizes and models intermediate (IM) state defects in MTJs; IM state manifests itself as an abnormal third resistive state, apart from the two bi-stable states of MTJ. We...

conference paper 2021

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Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs

Cardoso Medeiros, G. (author), Fieback, M. (author), Gebregiorgis, A.B. (author), Taouil, M. (author), Bolzani Poehls, L. (author), Hamdioui, S. (author)

Manufacturing defects in FinFET SRAMs can cause hard-to-detect faults such as Random Read Faults (RRFs). Detection of RRFs is not trivial, as they may not lead to incorrect outputs. Undetected RRFs become test escapes, which might lead to no-trouble-found devices and early in-field failures. Therefore, the detection of RRFs is of utmost...

conference paper 2021

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Intermittent Undefined State Fault in RRAMs

Fieback, M. (author), Cardoso Medeiros, G. (author), Gebregiorgis, A.B. (author), Aziza, Hassen (author), Taouil, M. (author), Hamdioui, S. (author)

Industry is prototyping and commercializing Resistive Random Access Memories (RRAMs). Unfortunately, RRAM devices introduce new defects and faults. Hence, high-quality test solutions are urgently needed. Based on silicon measurements, this paper identifies a new RRAM unique fault, the Intermittent Undefined State Fault (IUSF); this fault causes...

conference paper 2021

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Improving the Detection of Undefined State Faults in FinFET SRAMs

Cardoso Medeiros, G. (author), Fieback, M. (author), Copetti, Thiago (author), Gebregiorgis, A.B. (author), Taouil, M. (author), Bolzani Poehls, L. M. (author), Hamdioui, S. (author)

Manufacturing defects in FinFET SRAMs can cause hard-to-detect faults such as Undefined State Faults (USFs). Detection of USFs is not trivial, as they may not lead to incorrect functionality. Nevertheless, undetected USFs may have a severe impact on the memory's quality: they can cause random read outputs, which might lead to test escapes and no...

conference paper 2021

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A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs

Cardoso Medeiros, G. (author), Cem Gursoy, Cemil (author), Wu, L. (author), Fieback, M. (author), Jenihhin, Maksim (author), Taouil, M. (author), Hamdioui, S. (author)

Manufacturing defects can cause faults in FinFET SRAMs. Of them, easy-to-detect (ETD) faults always cause incorrect behavior, and therefore are easily detected by applying sequences of write and read operations. However, hard-to-detect (HTD) faults may not cause incorrect behavior, only parametric deviations. Detection of these faults is of...

conference paper 2020

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Defect and Fault Modeling Framework for STT-MRAM Testing

Wu, L. (author), Rao, Siddharth (author), Taouil, M. (author), Cardoso Medeiros, G. (author), Fieback, M. (author), Marinissen, Erik Jan (author), Kar, Gouri Sankar (author), Hamdioui, S. (author)

STT-MRAM mass production is around the corner as major foundries worldwide invest heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet cost-efficient test solutions are of great importance. This article presents a systematic device-aware defect and fault modeling framework for STT-MRAM to derive accurate...

journal article 2019

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Challenges and Solutions in Emerging Memory Testing

Vatajelu, E.I. (author), Prinetto, Paolo (author), Taouil, M. (author), Hamdioui, S. (author)

The research and prototyping of new memory technologies are getting a lot of attention in order to enable new (computer) architectures and provide new opportunities for today’s and future applications. Delivering high quality and reliability products was and will remain a crucial step in the introduction of new technologies. Therefore,...

journal article 2019

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A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

Cardoso Medeiros, G. (author), Bolzani Poehls, L.M. (author), Taouil, M. (author), Luis Vargas, F. (author), Hamdioui, S. (author)

Resistive defects in FinFET SRAMs are an important challenge for manufacturing test in submicron technologies, as they may cause dynamic faults, which are hard to detect and therefore may increase the number of test escapes. This paper presents a defect-oriented test that uses On-Chip Current Sensors (OCCSs) to detect weak resistive defects...

journal article 2018

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Yield and Cost Analysis or 3D Stacked ICs

Taouil, M. (author)

3D stacking is an emerging technology promising many benefits such as low latency between stacked dies, reduced power consumption, high bandwidth communication, improved form factor and package volume density, heterogeneous integration, and low-cost manufacturing. However, it requires modification of existing methods and/or introduction of new...

doctoral thesis 2014