A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <-54-dBc Spurs Under 50-mV _ppSupply Ripple

In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the...

A 590 μw, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC

This paper presents a continuous-Time zoom ADC for audio applications. It combines a 4-bit noise-shaping coarse SAR ADC and a fine delta-sigma modulator with a tail-resistor linearized OTA for improved linearity, energy efficiency, and handling of out-of-band interferers compared to previous designs. In 160 nm CMOS, the prototype chip...

A Pitch-Matched Transceiver ASIC With Shared Hybrid Beamforming ADC for High-Frame-Rate 3-D Intracardiac Echocardiography

In this article, an application-specific integrated circuit (ASIC) for 3-D, high-frame-rate ultrasound imaging probes is presented. The design is the first to combine element-level, high-voltage (HV) transmitters and analog front-ends, subarray beamforming, and in-probe digitization in a scalable fashion for catheter-based probes. The...

Versatile DAC-less successive approximation ADC architecture for medium speed data acquisition

Implementation of the DAC is usually the bottleneck in designing a SAR ADC. Here an innovative DAC-less SAR (DLSAR) ADC architecture is presented which alleviates some drawbacks of the conventional SAR counterpart. The proposed DLSAR binary search algorithm is comprised of two arithmetic operations of division-by-two and subtraction to...

A 7-bit 1-GSa/s Cryo-CMOS ADC for Spin-Qubit Readout

Quantum computing offers exponential speed-up for problems that are computationally intractable with classical computing. However, quantum processors with thousands to millions of quantum bits (qubits) are needed. Room-temperature electronics are used to control and readout today's qubits operating at cryogenic temperature. As the number of...

Calibration Techniques for Power-efficient Residue Amplifiers in Pipelined ADCs

Residue amplification plays a key role in determining the energy efficiency, area and performance of high-speed pipelined ADCs. At its core, a residue amplifier simply consists of four transistors that transfer a differential input voltage to a capacitive load with the desired gain. However, in order to ensure gain accuracy over PVT, the core...

A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW

This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta-sigma modulator (ΔΣM) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the...

A 10 bit 5 MS/s column SAR ADC with digital error correction for CMOS image sensors

This brief proposes a successive approximation register (SAR) analog-to-digital converter (ADC) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence...

A Continuous-Time Zoom ADC for Low-Power Audio Applications

This article presents a continuous-Time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-Time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive,...

Energy-Efficient Bridge-to-Digital Converters

This paper presents an overview of energy-efficient analog-to-digital converters (ADCs) specifically intended for the readout of Wheatstone bridge sensors. Apart from achieving good energy-efficiency, such bridge-to-digital converters (BDCs) must achieve low input-referred offset, drift and noise; high gain accuracy, stability and linearity;...

A 280 μW Dynamic Zoom ADC With 120 dB DR 118 dB SNDR in 1 kHz BW

This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (&amp;lt;1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential &amp;#x0394; &amp;#x03A3; ADC. Compared to previous zoom ADCs,...

A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier

This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mV_pp,diff and 4 × gain, it achieves-100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice...

A Charge-Redistribution Phase-Domain ADC Using an IQ-Assisted Binary-Search Algorithm

Phase-domain Analog-to-Digital Converters (Ph-ADCs) have been considered for power-efficient implementation of body-area network transceivers employing phase demodulation. Conventional implementations of the Ph-ADCs, which work based on a full-flash zero-crossing algorithm, use linear resistive/current combiners to determine the thermometer...

A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications

We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide range of operating conditions, including a harsh...

Analysis and Design of a 2.5GS/s 6-bit SAR ADC with a 3-bit/cycle Resolving Scheme

The thesis analyzes the design challenges that arise when developing high-speed ADCs and shows, through an extensive architecture study, that the SAR topology can be used with a sampling rate of 2.5GS/s if asynchronous processing and a multi-bit per cycle approach are adopted. The transistor-level implementation and simulation of a 6-bit SAR ADC...

A High-Resolution, Resistor-Based Temperature Sensor

This thesis focuses on developing a high-resolution, energy-efficient smart temperature sensor. A resistor-based temperature-sensing structure is chosen as the core of the sensor. To digitize the core output, a low-noise readout circuit is developed. The design was fabricated in a standard CMOS technology, and the measurements were conducted to...

Energy-Efficient Capacitive-Sensor Interface Based on A Multi-Slope ADC

This thesis presents an energy-efficient capacitive sensor interface based on a multi-slope analog-to-digital converter (ADC). This highly stable capacitance-to-digital converter (CDC) utilizes precision resistor as reference components. By utilizing a multi-slope analog-to-digital converter, the conversion time of this design is reduced down to...

A Gm-C Continuous-Time Sigma-Delta Modulator with Improved Linearity

Bridge sensors are widely used for accurate measurement of physical quantities such as temperature, pressure, strain or altitude. Such sensors require a low-noise, high-resolution and accurate readout system with high input impedance. In order to meet these requirements, conventional sensor readout systems use multiple stages which typically...