Searched for: subject%3A%22analog%255C-to%255C-digital%255C%2Bconverter%22
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Niu, Yunfan (author), Mo, J. (author), May, Alexander (author), Rommel, Mathias (author), Rossi, Chiara (author), Romijn, J. (author), Zhang, Kouchi (author), Vollebregt, S. (author)
This work presents the design and characterization of an analog-to-digital converter (ADC) with silicon carbide (SiC) for sensing applications in harsh environments. The SiC-based ADC is implemented with the state-of-the-art low-voltage SiC complementary-metal-oxide-semiconductor (CMOS) technology developed by Fraunhofer IISB. Two types of...
conference paper 2023
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Singh, A. (author), Bishnoi, R.K. (author), Kaichouhi, A. (author), Diware, S.S. (author), Joshi, R.V. (author), Hamdioui, S. (author)
Analog computation-in-memory (CIM) architecture alleviates massive data movement between the memory and the processor, thus promising great prospects to accelerate certain computational tasks in an energy-efficient manner. However, data converters involved in these architectures typically achieve the required computing accuracy at the expense...
conference paper 2023
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Kiene, G. (author), Overwater, R.W.J. (author), Catania, Alessandro (author), Gunaputi Sreenivasulu, A.M. (author), Bruschi, Paolo (author), Charbon-Iwasaki-Charbon, E. (author), Babaie, M. (author), Sebastiano, F. (author)
This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6-8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multiplexed input in a spin-qubit reflectometry readout for quantum computing. To optimize the...
journal article 2023
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Chen, Y. (author), Gong, J. (author), Staszewski, R.B. (author), Babaie, M. (author)
In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the...
journal article 2022
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Hopf, Y.M. (author), Ossenkoppele, Boudewine W. (author), Soozande, Mehdi (author), Noothout, E.C. (author), Chang, Z.Y. (author), Chen, Chao (author), Vos, H.J. (author), Bosch, Johan G. (author), Verweij, M.D. (author), de Jong, N. (author), Pertijs, M.A.P. (author)
In this article, an application-specific integrated circuit (ASIC) for 3-D, high-frame-rate ultrasound imaging probes is presented. The design is the first to combine element-level, high-voltage (HV) transmitters and analog front-ends, subarray beamforming, and in-probe digitization in a scalable fashion for catheter-based probes. The...
journal article 2022
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Pourahmad, Ali (author), Dehghani, Rasoul (author), Ahmadi-Mehr, Seyed Amir-Reza (author), Lotfi, R. (author)
Implementation of the DAC is usually the bottleneck in designing a SAR ADC. Here an innovative DAC-less SAR (DLSAR) ADC architecture is presented which alleviates some drawbacks of the conventional SAR counterpart. The proposed DLSAR binary search algorithm is comprised of two arithmetic operations of division-by-two and subtraction to...
journal article 2022
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Mehrotra, Shubham (author), Eland, Efraim (author), Karmakar, S. (author), Liu, Angqi (author), Gonen, B. (author), Bolatkale, M. (author), Van Veldhoven, Robert (author), Makinwa, K.A.A. (author)
This paper presents a continuous-Time zoom ADC for audio applications. It combines a 4-bit noise-shaping coarse SAR ADC and a fine delta-sigma modulator with a tail-resistor linearized OTA for improved linearity, energy efficiency, and handling of out-of-band interferers compared to previous designs. In 160 nm CMOS, the prototype chip...
conference paper 2022
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GUNAPUTI SREENIVASULU, Aishwarya (author)
Quantum computing offers exponential speed-up for problems that are computationally intractable with classical computing. However, quantum processors with thousands to millions of quantum bits (qubits) are needed. Room-temperature electronics are used to control and readout today's qubits operating at cryogenic temperature. As the number of...
master thesis 2021
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Sehgal, R.K. (author)
Residue amplification plays a key role in determining the energy efficiency, area and performance of high-speed pipelined ADCs. At its core, a residue amplifier simply consists of four transistors that transfer a differential input voltage to a capacitive load with the desired gain. However, in order to ensure gain accuracy over PVT, the core...
doctoral thesis 2021
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Eland, E.N. (author), Karmakar, S. (author), Gonen, B. (author), van Veldhoven, Robert (author), Makinwa, K.A.A. (author)
This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta-sigma modulator (ΔΣM) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the...
journal article 2021
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Xie, S. (author), Theuwissen, A.J.P.A.M. (author)
This brief proposes a successive approximation register (SAR) analog-to-digital converter (ADC) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence...
journal article 2020
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Gonen, B. (author), Karmakar, S. (author), van Veldhoven, Robert (author), Makinwa, K.A.A. (author)
This article presents a continuous-Time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-Time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive,...
journal article 2020
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Akter, S. (author), Makinwa, K.A.A. (author), Bult, K. (author)
This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mV<sub>pp,diff</sub> and 4 × gain, it achieves-100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice...
journal article 2018
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Karmakar, S. (author), Gonen, B. (author), Sebastiano, F. (author), van Veldhoven, Robert (author), Makinwa, K.A.A. (author)
This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (&amp;lt;1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential &amp;#x0394; &amp;#x03A3; ADC. Compared to previous zoom ADCs,...
journal article 2018
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Jiang, H. (author), Makinwa, K.A.A. (author)
This paper presents an overview of energy-efficient analog-to-digital converters (ADCs) specifically intended for the readout of Wheatstone bridge sensors. Apart from achieving good energy-efficiency, such bridge-to-digital converters (BDCs) must achieve low input-referred offset, drift and noise; high gain accuracy, stability and linearity;...
conference paper 2018
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Rajabi, Leila (author), Saberi, Mehdi (author), Liu, Y. (author), Lotfi, R. (author), Serdijn, W.A. (author)
Phase-domain Analog-to-Digital Converters (Ph-ADCs) have been considered for power-efficient implementation of body-area network transceivers employing phase demodulation. Conventional implementations of the Ph-ADCs, which work based on a full-flash zero-crossing algorithm, use linear resistive/current combiners to determine the thermometer...
journal article 2017
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Homulle, Harald (author), Visser, S.M.C. (author), Charbon-Iwasaki-Charbon, E. (author)
We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmware. Therefore it can be used in a wide range of operating conditions, including a harsh...
journal article 2016
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Ursulean, M. (author)
The thesis analyzes the design challenges that arise when developing high-speed ADCs and shows, through an extensive architecture study, that the SAR topology can be used with a sampling rate of 2.5GS/s if asynchronous processing and a multi-bit per cycle approach are adopted. The transistor-level implementation and simulation of a 6-bit SAR ADC...
master thesis 2016
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Luo, Y. (author)
This thesis focuses on developing a high-resolution, energy-efficient smart temperature sensor. A resistor-based temperature-sensing structure is chosen as the core of the sensor. To digitize the core output, a low-noise readout circuit is developed. The design was fabricated in a standard CMOS technology, and the measurements were conducted to...
master thesis 2015
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Cheng, Y. (author)
This thesis presents an energy-efficient capacitive sensor interface based on a multi-slope analog-to-digital converter (ADC). This highly stable capacitance-to-digital converter (CDC) utilizes precision resistor as reference components. By utilizing a multi-slope analog-to-digital converter, the conversion time of this design is reduced down to...
master thesis 2012
Searched for: subject%3A%22analog%255C-to%255C-digital%255C%2Bconverter%22
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