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Yanik, K.I.M. (author)
The trend of increasing performance by parallelism is followed by the adoption of heterogeneous systems. In order to allow more fine-tuned balancing between used thread- and instruction level parallelism, the heterogeneous ρ-VEX platform was developed. Pipelining has been a part of microprocessor development for decades to increase throughput of...
master thesis 2016
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Rovers, A. (author)
Vario-scale data structures make it possible to derive maps at arbitrary scale. When requesting a map, data has to be transferred from server to client. This takes time, which affects the responsiveness of the system, and sometimes costs can be involved for every byte that is send over the network. Redundant data transfers should thus be avoided...
master thesis 2016
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Van Straten, J. (author)
This thesis describes the design and implementation of a VLIW processor and associated caches based on the ρ-VEX concept. An ρ-VEX processor must be dynamically (runtime) reconfigurable to behave as a single large processor, two medium-sized processors, or four small processors. This allows a scheduler to optimize for energy and/or performance...
student report 2016
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Ampntel-Kanter-Oikonomou, A.K. (author)
Nowadays, modern Integrated Circuit (IC) technology allows processor manufacturers to produce complex designs with up to a few billions of transistors.Technology limitations and the end of voltage and frequency scaling forced computer architecture to multicore designs and more specialized solutions on hardware. These technology trends increased...
master thesis 2015
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Zuidema, E. (author)
In the online travel environment it is physically and economically not possible to retrieve the hotel room rates in real-time for every customer request. To overcome this problem the hotel rates are cached, but due to the fact that the suppliers will not send notifications of price changes it is a challenging task to keep the cache up to date....
master thesis 2012
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Roostaie, V. (author)
Cache coherence and memory consistency are of the most decisive and challenging issues in the design of shared-memory multi-core systems that influence both the correctness and performance of parallel programs. In this thesis, we identify and analyze the problem of designing a coherent/consistent memory subsystem in general and then focus on...
master thesis 2011
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Xu, S. (author), Xue, W. (author), Lin, H.X. (author)
In this article, we discuss the performance modeling and optimization of Sparse Matrix-Vector Multiplication (SpMV) on NVIDIA GPUs using CUDA. SpMV has a very low computation-data ratio and its performance is mainly bound by the memory bandwidth. We propose optimization of SpMV based on ELLPACK from two aspects: (1) enhanced performance for the...
journal article 2011
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Pereira de Azevedo Filho, A. (author)
In this dissertation we present methodologies and evaluations aiming at increasing the efficiency of video coding applications for heterogeneous many-core processors composed of SIMD-only, scratchpad memory based cores. Our contributions are spread in three different fronts: thread-level parallelism strategies for many-cores, identification of...
doctoral thesis 2011
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Strydis, C. (author)
HEALTHCARE in the 21st century is changing rapidly. In advanced countries, in particular, healthcare is moving from a public to a more personalized nature. However, the costs of healthcare worldwide are increasing every year. Better use of technology can and should be used to get control of these costs. At the same time, implants have clearly...
doctoral thesis 2011
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De Langen, P.J. (author)
doctoral thesis 2009
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Molnos, A.M. (author)
doctoral thesis 2009
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Shahbahrami, A. (author)
In this dissertation, a novel SIMD extension called Modified MMX (MMMX) for multimedia computing is presented. Specifically, the MMX architecture is enhanced with the extended subwords and the matrix register file techniques. The extended subwords technique uses SIMD registers that are wider than the packed format used to store the data. The...
doctoral thesis 2008
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Al-Ars, Z. (author), Hamdioui, S. (author), Gaydadjiev, G. (author), Vassiliadis, S. (author)
Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transistors dedicated to such memories. This paper discusses the methodology used to develop effective and efficient cache tests, and the way it is implemented to optimize...
journal article 2008
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Shahbahrami, A. (author), Juurlink, B. (author), Vassiliadis, S. (author)
The 2-D Discrete Wavelet Transform (DWT) consumes up to 68% of the JPEG2000 encoding time. In this paper, we develop efficient implementations of this important kernel on general-purpose processors (GPPs), in particular the Pentium 4 (P4). Efficient implementations of the 2-D DWT on the P4 must address three issues. First, the P4 suffers from a...
journal article 2008
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