Optimistic No-regret Algorithms for Discrete Caching

We take a systematic look at the problem of storing whole files in a cache with limited capacity in the context of optimistic learning, where the caching policy has access to a prediction oracle. The successive file requests are assumed to be generated by an adversary, and no assumption is made on the accuracy of the oracle. We provide a...

Online Caching with no Regret: Optimistic Learning via Recommendations

The design of effective online caching policies is an increasingly important problem for content distribution networks, online social networks and edge computing services, among other areas. This paper proposes a new algorithmic toolbox for tackling this problem through the lens of optimistic online learning. We build upon the Follow-the...

Quid pro Quo in Streaming Services: Algorithms for Cooperative Recommendations

Recommendations are employed by Content Providers (CPs) of streaming services in order to boost user engagement and their revenues. Recent works suggest that nudging recommendations towards cached items can reduce operational costs in the caching networks, e.g., Content Delivery Networks (CDNs) or edge cache providers in future wireless...

Elastic FemtoCaching: Scale, Cache, and Route

The advent of elastic Content Delivery Networks (CDNs) enable Content Providers (CPs) to lease cache capacity on demand and at different cloud and edge locations in order to enhance the quality of their services. This article addresses key challenges in this context, namely how to invest an available budget in cache space in order to match...

Hash-based hierarchical caching and layered filtering for interactive previews in global illumination rendering

Modern Monte-Carlo-based rendering systems still suffer from the computational complexity involved in the generation of noise-free images, making it challenging to synthesize interactive previews. We present a framework suited for rendering such previews of static scenes using a caching technique that builds upon a linkless octree. Our...

Using a generic spatial access method for caching and efficient retrieval of vario-scale data in a server-client architecture

This paper presents a methodology for using a generic data-driven spatial access method as a communication mechanism for vario-scale data in a server-client setting. As a complete data set is often quite large, it is managed at the server side and supporting different scale levels is important. We show that a generic R-tree like grouping method,...

Performance modeling and optimization of sparse matrix-vector multiplication on NVIDIA CUDA platform

In this article, we discuss the performance modeling and optimization of Sparse Matrix-Vector Multiplication (SpMV) on NVIDIA GPUs using CUDA. SpMV has a very low computation-data ratio and its performance is mainly bound by the memory bandwidth. We propose optimization of SpMV based on ELLPACK from two aspects: (1) enhanced performance for the...

Efficient Execution of Video Applications on Heterogeneous Multi- and Many-Core Processors

In this dissertation we present methodologies and evaluations aiming at increasing the efficiency of video coding applications for heterogeneous many-core processors composed of SIMD-only, scratchpad memory based cores. Our contributions are spread in three different fronts: thread-level parallelism strategies for many-cores, identification of...

Universal Processor Architecture for Biomedical Implants: The SiMS Project

HEALTHCARE in the 21st century is changing rapidly. In advanced countries, in particular, healthcare is moving from a public to a more personalized nature. However, the costs of healthcare worldwide are increasing every year. Better use of technology can and should be used to get control of these costs. At the same time, implants have clearly...

Energy reduction techniques for caches and multiprocessors

Task centric memory management for an on-chip multiprocessor

Avoiding conversion and rearrangement overhead in SIMD architecures

In this dissertation, a novel SIMD extension called Modified MMX (MMMX) for multimedia computing is presented. Specifically, the MMX architecture is enhanced with the extended subwords and the matrix register file techniques. The extended subwords technique uses SIMD registers that are wider than the packed format used to store the data. The...

Test Set Development for Cache Memory in Modern Microprocessors

Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transistors dedicated to such memories. This paper discusses the methodology used to develop effective and efficient cache tests, and the way it is implemented to optimize...

Implementing the 2-D Wavelet Transform on SIMD-Enhanced General-Purpose Processors

The 2-D Discrete Wavelet Transform (DWT) consumes up to 68% of the JPEG2000 encoding time. In this paper, we develop efficient implementations of this important kernel on general-purpose processors (GPPs), in particular the Pentium 4 (P4). Efficient implementations of the 2-D DWT on the P4 must address three issues. First, the P4 suffers from a...