DLL Based Single Slope ADC For CMOS Image Sensor Column Readout

This thesis presents a Delay Locked Loop(DLL) based Single Slope ADC. Compared to the convertional Single Slope ADC, the readout speed is increased by 16 times. A DLL is designed with a start-controlled Phase Frequency Detector (PFD), a differential ended Charge Pump (CP) and fully differential Delay Cells (DC). The multi-stage comparator with...

Bit-error rate measurement setup and comparator design

Bit-error rate (BER) of comparators is becoming one of the limiting factors in the design of high speed ADCs. BER measurement setup is introduced and implemented in this thesis. Using this BER measurement setup gives us the opportunity to compare the BER of different comparators. It also enables us to study the effect of different parameters...