Searched for: subject%3A%22digital%255C-to%255C-time%255C%2Bconverter%255C%2B%255C%2528DTC%255C%2529%22
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Gao, Z. (author)
Reducing power consumption is becoming increasingly important for the sustainability of the communication industry because it is expected to consume a significant portion of the global electricity in the face of the exponentially increasing demands on the volume and rate of data transmission. As the scope narrows to the individual wireless...
doctoral thesis 2023
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Gao, Z. (author), He, J. (author), Fritz, Martin (author), Shen, Y. (author), Zong, Z. (author), Spalink, Gerd (author), Alavi, S.M. (author), Staszewski, R.B. (author), Babaie, M. (author)
This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO)...
journal article 2023
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Liu, Bangan (author), Zhang, Yuncheng (author), Qiu, Junjun (author), Ngo, Huy Cu (author), Deng, Wei (author), Nakata, Kengo (author), Yoshioka, Toru (author), Emmei, Jun (author), Pang, Jian (author), Someya, T. (author)
In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-N multiplying delay-locked loop,(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To...
journal article 2021
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Chen, Peng (author), Zhang, Feifei (author), Zong, Z. (author), Hu, Suoping (author), Siriburanon, Teerachot (author), Staszewski, R.B. (author)
This article proposes a power-efficient highly linear capacitor-array-based digital-to-time converter (DTC) using a charge redistribution constant-slope approach. A fringe-capacitor-based digital-to-analog converter (C-DAC) array is used to regulate the starting supply voltage of the constant discharging slope fed to a fixed-threshold...
journal article 2019
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Zong, Z. (author), Chen, Peng (author), Staszewski, R.B. (author)
In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f <sup>3</sup> ) and thermal (1/f <sup>2</sup> ) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong...
journal article 2019
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Chen, Peng (author), Huang, Xiongchuan (author), Chen, Y. (author), Wu, Lianbo (author), Staszewski, R.B. (author)
To characterize an on-chip programmable delay in a low-cost and high-resolution manner, a built-in self-test based on a first-order &amp;#x0394;&amp;#x03A3; time-to-digital converter with self-calibration is proposed and implemented in TSMC 28-nm CMOS. The system is self-contained, and only one digital clock is needed for the measurements. A...
journal article 2018
Searched for: subject%3A%22digital%255C-to%255C-time%255C%2Bconverter%255C%2B%255C%2528DTC%255C%2529%22
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